Hi Michael,
Which version (git commit and fork) of mlib_devel did you use to compile
your bitcode?
Which version (git commit and fork) of the adc5g library are you using?
What does the output of the following command show for the affected ADC
after test mode has been unset?
>>>
Hi Amit,
Unfortunately the way the routine is written it requires two snapshot
blocks when the board is configured for dual channel mode, one for each
snapshot. The names of the snapshots are then passed in a list to the
function, as an example:
>>> adc5g.calibrate_mmcm_phase(roach2, zdok_n,
lot
>
> Guenter
>
>
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
> *Sent:* Donnerstag, 25. August 2016 17:05
> *To:* Guenter Knittel; Primiani, Rurik
> *Cc:* casper list
> *Subject:* Re: [casper] Glitches in ADC-data
>
>
>
> Hi Guenter,
>
t;
> So I guess I need some more provisions for using this method. I checked
> using planAhead
>
> if there are IODELAYs in the FPGA design, and indeed there are, but maybe
> I need some
>
> additional interface units?
>
>
>
> Thanks
>
> Guenter
>
>
>
>
>
> *Fro
Hi Heystek,
In addition to what Jack suggests it looks like you may have copied
"tutorial1.slx" to a new model called "tutorial1a.slx" and then immediately
tried to run the casper_xps. From my experience when this is done some of
the gateway in/out blocks do not have a chance to change their
Hi Guenter,
At the SMA we also see glitches sampling at ~4600 MHz. Interestingly we do
not see any glitches at all when switched to test ramp mode even when
looking at very long snapshots. For us running a second MMCM calibration
after both the ADC and FPGA chips get a chance to warm up seems to
th 1:1 DEMUX
>>> mode) at 160 MHz. I see the zdok1 snapshot data shows no data whatsoever
>>> while snapshot from zdok0 is fine. The MMCM also fails for zdok1.
>>>
>>> Have you successfully ran fpga at lower frequencies ?
>>>
>>> Cheers,
>>>
--
> Ran 8 tests in 7.230s
>
> FAILED (failures=1)
>
> Please let me know if I am doing anything wrong or where could be the
> problem.
>
> For your information:
>
> System: roach2
>
> ADC : ASIAA ADC5G ADC
>
> Clock : 2
Hi Michael,
Which exact mlib_devel commit from which fork are you using?
I believe this was fixed in commit sma-wideband/mlib_devel@404989f on June
27, 2014. See the github link here:
https://github.com/sma-wideband/mlib_devel/commit/404989f
It's possible this somehow did not make it to the
Hi Tim,
The rev2 and rev1 pinouts are *not* the same; specifically some ZDOK pins
were changed likely the errors you have found.
You should not be using hw_routes_roach2rev1.mat if you have a rev2. You
should be using hw_routes.mat.
Best,
Rurik
On Wed, Apr 29, 2015 at 10:58 AM, Madden, Timothy
:01 PM, Primiani, Rurik wrote:
What version of mlib_devel are you using?
On Tue, Oct 21, 2014 at 4:56 PM, Amit Bansod aban...@mpifr-bonn.mpg.de
mailto:aban...@mpifr-bonn.mpg.de wrote:
Dear All,
While testing the design from 5g ADC clock (adc0_clk) at 100 MHz, I am
getting
Hi Tom,
I think you need to use rww_tools.set_zdok(1) if you want to adjust ZDOK1,
and of course set it back to 0 when you want to adjust ZDOK0.
Best,
Rurik
On Fri, Sep 12, 2014 at 3:22 PM, Geelen, T.F.G. t.f.g.gee...@student.tue.nl
wrote:
Hi Jonathan,
Sorry for the confusion, describing a
: vrijdag 4 juli 2014 17:15
Aan: Geelen, T.F.G.
Onderwerp: Fwd: [casper] Fwd: ADC 5GS error in ROACH2
-- Forwarded message --
From: Primiani, Rurik rprimi...@cfa.harvard.edumailto:
rprimi...@cfa.harvard.edumailto:rprimi...@cfa.harvard.edumailto:
rprimi...@cfa.harvard.edu
Date: 2014
[andres.alve...@gmail.commailto:
andres.alve...@gmail.commailto:andres.alve...@gmail.commailto:
andres.alve...@gmail.com]
Verzonden: vrijdag 4 juli 2014 17:15
Aan: Geelen, T.F.G.
Onderwerp: Fwd: [casper] Fwd: ADC 5GS error in ROACH2
-- Forwarded message --
From: Primiani, Rurik rprimi
Hi Ho-Cheung,
At present, the sync signal can only be supplied by the FPGA, the external
sync input is wired directly to the FPGA on the board (i.e. not to the ADC
chip). Generally the start-up procedure is to set the ADC into test ramp
mode, sync it, and the use the ramp to calibrate the MMCM.
Hi Raul,
What errors are you getting?
Which version of mlib_devel did you use to compile your bof file?
Do you have a snapshot attached to the ADC output that properly converts
offset binary to signed two's?
Jack Hickish has some great code that aligns the data window using IODELAYS
instead of
Hi Jack,
That rate is for the -1L speed grade, this is the lower power option.
As far as I know the standard speed grade is the -1 which is quoted
to support 1.25 Gbps DDR.
Best,
Rurik
On Mon, Jun 2, 2014 at 6:17 PM, Jack Hickish jackhick...@gmail.com wrote:
Howdy,
The wiki says the ADC5g
Hi Gopal,
The MMCM error you pasted above has nothing to do with the ADC5g
block. It is instead coming from the roach_infrastructure pcore which
generates the sys_clk signal. What are your XSG core config mask
parameters set to?
I'm not sure how the sma_wideband repository differs from ska-sa in
Tool: XST
Yes, I normally use the ska-sa branch, and I have compiled the tutorial 3
spectrometer using other boards (KatADC or iADC) successfully without
needing the Fixed point Toolbox.
Thanks!
Gopal
On Fri, May 9, 2014 at 2:24 PM, Primiani, Rurik rprimi...@cfa.harvard.edu
wrote:
Hi
Yes, Dave, I think you're right.
I'm unclear why the sys_clk MMCM doesn't just have hard-coded clock
factors. Its input clock never changes and it's always outputting 100
MHz and 200 MHz.
On the other hand, the aux_clk MMCM does seem to have its factors
hard-coded even though aux_clk can be an
Hi Andres,
Which version of mlib_devel are you using?
Thanks,
Rurik
On Wed, May 7, 2014 at 3:43 PM, Andres Alvear andres.alve...@gmail.com wrote:
I am trying to compile a wideband spectrometer (like in tutorial 3) for
ROACH 2, using a ADC1x5000-8 in the 1:1 demux version.
I'm using the
:
Hi Rurik,
I am using Xilinx 14.5 version and the last time I updated the libraries was
november 2013.
Do you think that's the problem?
Thanks,
Andres
2014-05-07 15:48 GMT-04:00 Primiani, Rurik rprimi...@cfa.harvard.edu:
Hi Andres,
Which version of mlib_devel are you using
rev-parse --short HEAD
a8c43a8
root@roach-MS-7845:/opt/mlib_devel# git remote -v
origingit://github.com/ska-sa/mlib_devel.git (fetch)
origingit://github.com/ska-sa/mlib_devel.git (push)
Thanks,
Andres
2014-05-07 16:01 GMT-04:00 Primiani, Rurik rprimi...@cfa.harvard.edu:
Hi Andres
Hi Rolando,
I suspect Dan may have been referring to the PhRInGES system developed
for VLBI at the SMA and CARMA; it's a phased array with two iBOBs that
sample four inputs each, coherently sum them, and send the sum to a
third iBOB over XAUI links for the final sum (total of 8 inputs).
There is
Hi Norbert,
I believe the field you're looking for is 'hw_sys'. I think your
gen_ucf code will work if you change the following line:
board = blk_obj.board;
to:
board = blk_obj.hw_sys;
Best,
Rurik
On Thu, Feb 6, 2014 at 11:13 AM, Norbert Bonnici
norbert.bonnici...@um.edu.mt wrote:
Hi Wes,
at to fix the
problem? Thanks!
Weiwei
On Thu, Jan 30, 2014 at 4:04 PM, Jack Hickish jackhick...@gmail.com wrote:
On 30 January 2014 23:56, Primiani, Rurik rprimi...@cfa.harvard.edu
wrote:
Hi Weiwei,
Have you calibrated the MMCM phase using test vectors? The following
repository hosts
Hi Weiwei,
Have you calibrated the MMCM phase using test vectors? The following
repository hosts Python/corr code that may be helpful to you:
https://github.com/sma-wideband/adc_tests
I've recently updated the README, please see the Calibrating the
data-to-clk for instructions on how to use the
advice on the maillist might be worthwhile. If anyone has
any words of wisdom, I'd be excessively grateful to hear from them.
Cheers,
Jack
On 6 November 2013 16:31, Primiani, Rurik rprimi...@cfa.harvard.edu wrote:
Hi Weiwei,
Generally the sma-wideband/mlib_devel has the most recent changes
Hi Weiwei,
Firstly, I am assuming you're using the DMUX 1:1 ASIAA adc5g yellow
block. To use LOW bandwidth mode, you will need to change line 362
in the following file:
should not move the pblocks, and come out other way to meet the
timing.
Weiwei
On Wed, Nov 6, 2013 at 10:11 AM, Primiani, Rurik rprimi...@cfa.harvard.edu
wrote:
Hi Weiwei,
In most cases, as long as you run your design below the
successfully-compiled-for clock rate, i.e. the clock rate
about the option 3: How does the fpga/adc
actually work if the design and running are at different clock rate?
Thanks very much Rurik! Your suggestions are really helpful to me to dig
into the problem.
Weiwei
On Wed, Nov 6, 2013 at 8:31 AM, Primiani, Rurik rprimi...@cfa.harvard.edu
wrote
Hi,
Which version of mlib_devel are you using?
Rurik
On Tue, Nov 5, 2013 at 11:16 PM, Weiwei Sun su...@uw.edu wrote:
Hi,
I have trouble to compile the adc clock rate of asiaa_adc5g block at
2500MHz.
Block parameter: two-channel, ZDOK0, demux 1:1 .
System: roach2, clock source:adc0_clk,
Hi Katty,
This is my fault. I added some pins (and other things) to the ASIAA
ADC pcore for ROACH-2 that are not available on ROACH-1. I'll submit a
fix for this to sma-wideband/mlib_devel but a quick way to prevent
this error is to delete lines 270-272 of
Hi JP,
We recently (last week) discovered we desperately need the DDR3 on ROACH2
since our work-around for getting the visibility data out of our system
won't work in the long run (due to 10 GbE switch limiations... it's a long
story). So just this week I re-started work on a DDR3 yellow block I
Hi Andrew,
I tried the recent changes to Shared BRAM on ska-sa but I ran into an
error during Update Diagram in munge_init.m resulting from commit
2c13dab where it's trying to index div_size which is just a integer. I
attach a patch which fixes this issue; however I'm now running into
another
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