Re: [casper] ADC calibration issue

Probably not, but the calibration is bitstream dependent. You've probably found an edge case where the software fails, but it only occurs in one of your designs. In any case, it's good to know the hardware is ok. Cheers Jack On Thu, 30 Mar 2017 at 13:43 vijay kumar

Re: [casper] ADC calibration issue

Actually in my design, i am trying to capture adc values into a bram with adress with '16' and data width '8' . When I try to reduce the bram address widht to '8', this issue doesnt occur and adc calibration works fine. Is there anything wrong in the way I configure the brams ? On Thu, Mar 30,

Re: [casper] ADC calibration issue

The following is output I get when i type the 'git rev-parse HEAD': a949c9d5c1761078b4c884699ff52c1497a17ff6 On Thu, Mar 30, 2017 at 2:32 PM, Mark Wagner wrote: > git rev-parse HEAD > > On Thu, Mar 30, 2017 at 10:46 AM, Jack Hickish > wrote: > >> Someone

Re: [casper] ADC calibration issue

git rev-parse HEAD On Thu, Mar 30, 2017 at 10:46 AM, Jack Hickish wrote: > Someone better with git can tell you the "right" way, but I would just run > "git log" in the repository directory, and note the most recent commit hash. > > Cheers > Jack > > On Thu, 30 Mar 2017

Re: [casper] ADC calibration issue

Someone better with git can tell you the "right" way, but I would just run "git log" in the repository directory, and note the most recent commit hash. Cheers Jack On Thu, 30 Mar 2017 at 10:31 vijay kumar wrote: > I am using 200 MHz ADC clock frequency (demux-1).

Re: [casper] ADC calibration issue

I am using 200 MHz ADC clock frequency (demux-1). And I am not sure how to check the adc repo and mlib_devel repo versions ? Could you please help me in that ? Thank you. On Wed, Mar 29, 2017 at 6:39 PM, Jack Hickish wrote: > I like the triumphant "done!" at the end :) >

Re: [casper] ADC calibration issue

I like the triumphant "done!" at the end :) Next questions -- What version of the adc repo and mlib_devel repos are you using? Do you have other hardware you can test on? (It's very unlikely to be a hardware problem, IMO, but worth checking if you can). What ADC clock rate are you using? Cheers

Re: [casper] ADC calibration issue

Yes ! I assume the clock has been clocked. For convenience, I have included the output script i get after I run the initialization script. Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz... Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2) Gateware supports demux modes

Re: [casper] ADC calibration issue

Further, is the board clocking OK? -- I believe the initialization script should give feedback on whether of not the FPGA's PLL has successfully locked to the ADC clock, and what the current measured board clock is. Cheers Jack On Wed, 29 Mar 2017 at 14:28 Matt Dexter

Re: [casper] ADC calibration issue

Is the design and lab setup consistent with the limitations documented at https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations ? More information on the clock requirements may be found at