Re: [casper] Configuring 40GbE Yellow Block in JASPER

[Peryer, Mark A.]

Hello,

I have solved my issue of not being able to receive data. Instead of
directly connecting the SKARABs, I routed them through a 40 GbE switch
where the DHCP server can assign both of the SKARABs an IP address. I am
still not sure why directly connecting them does not work, however that
appears to be what was causing the issue all along.

Thanks for your help,

Mark

On Wed, Jul 5, 2017 at 4:20 PM, Peryer, Mark A. <mark.per...@cfa.harvard.edu
> wrote:

> Hello,
>
> I am still having issues receiving data over 40 GbE. I currently have a
> direct connection between the transmitting and receiving SKARABs, both on
> the leftmost 40 GbE port of Mezzanine slot 3 . Using tcpdump on a server
> with a 40GbE interface, I was able to confirm that the SKARAB which
> transmits data is successfully doing so. Also, both SKARABs can
> successfully be pinged over 40GbE. Despite this, I am still unable to
> receive data on the other SKARAB, even when Promiscuous Mode is enabled. I
> did observe that the orange and green LEDs are turned on for both of the
> SKARAB's 40GbE ports. The green light blinks on the SKARAB that is
> transmitting data and the orange light blinks on the SKARAB that is
> receiving data, therefore it appears they are communicating with each
> other.
>
> Any other suggestions on how to debug the reception data over 40 GbE would
> be much appreciated, as I am still unsure what could be causing the issue.
>
> Thanks,
>
> Mark
>
> On Fri, Jun 30, 2017 at 3:57 AM, Paul Prozesky <paul.proze...@gmail.com>
> wrote:
>
>> Morning Mark
>>
>> Please have a look here for SKARAB 40gbe TX and RX models with demo
>> software.
>>
>> https://github.com/ska-sa/mkat_fpga/tree/devel/source/skarab_dev/tut2
>>
>> Cheers
>> Paul
>>
>>
>> On 30 June 2017 at 07:46, Jason Manley <jman...@ska.ac.za> wrote:
>>
>>> Hi Mark
>>>
>>> The current SKARAB 40G yellowblock is a bit of a hack.
>>>
>>>   1) It is currently not parameterised, and is hard-coded for the first
>>> port on Mezzanine slot 3.
>>>
>>>   2) The tx_valid and rx_valid lines are 4-bits wide, not 1 bit. This
>>> will be rectified soon, but in the meanwhile, just feed the value "3" to
>>> tx_valid to send packets.
>>>
>>>   3) Note that there was a recent change to the TX and RX 64-bit word
>>> ordering (was previously incorrectly swapped). Make you built your
>>> bitstreams with a recent git checkout.
>>>
>>> It's on our todo list to get it properly parameterised and to fix the
>>> 4-bit weirdness, but it's not clear when we'll have that done.  In the
>>> meanwhile, the 40G does work, and we are successfully using this first port
>>> actively at SKA-SA.
>>>
>>> Some things you should try to help debug:
>>>
>>>   1) The microblaze will attempt to DHCP on the 40G interface. Did it
>>> obtain a lease? Check your DHCP server logs.
>>>
>>>   2) Check (using casperfpga software) that the cores are actually
>>> configured like you think. There was a version of microblaze that overwrote
>>> things. And if it's DHCP'ing (this is how we use the ports), then the IP
>>> will have changed from what you expect. 
>>> myfpgaobject.gbes['my_forty_gbe_core'].print_core_details()
>>> (or g.get_core_details()).
>>>
>>>   3) What does tcpdump/wireshark show is coming out of the TX board?
>>>
>>>   4) Did you select different MAC addresses for the "hardcoded"
>>> yellowblocks on the TX and RX side? Else a switch might not forward the
>>> packets.
>>>
>>>   5) Can you ping both 40G interfaces from a computer?
>>>
>>> Jason Manley
>>> CBF Manager
>>> SKA-SA
>>>
>>> Cell: +27 82 662 7726 <+27%2082%20662%207726>
>>> Work: +27 21 506 7300 <+27%2021%20506%207300>
>>>
>>> On 29 Jun 2017, at 20:37, Peryer, Mark A. <mark.per...@cfa.harvard.edu>
>>> wrote:
>>>
>>> > Hello,
>>> >
>>> > I am trying to send data from one SKARAB to another SKARAB over 40GbE.
>>> I have created two separate JASPER files, one for receiving and one for
>>> transmitting. Each design has one forty_gbe yellow block and are configured
>>> similar to Tutorial 2 on the casper website. In the JASPER file used for
>>> transmitting, I have placed a snapshot block on the tx_data signal for the
>>> forty_gbe block and am able to read the correct data from the snapshot
>>> block using casperf

Re: [casper] Configuring 40GbE Yellow Block in JASPER

[Peryer, Mark A.]

Hello,

I am still having issues receiving data over 40 GbE. I currently have a
direct connection between the transmitting and receiving SKARABs, both on
the leftmost 40 GbE port of Mezzanine slot 3 . Using tcpdump on a server
with a 40GbE interface, I was able to confirm that the SKARAB which
transmits data is successfully doing so. Also, both SKARABs can
successfully be pinged over 40GbE. Despite this, I am still unable to
receive data on the other SKARAB, even when Promiscuous Mode is enabled. I
did observe that the orange and green LEDs are turned on for both of the
SKARAB's 40GbE ports. The green light blinks on the SKARAB that is
transmitting data and the orange light blinks on the SKARAB that is
receiving data, therefore it appears they are communicating with each
other.

Any other suggestions on how to debug the reception data over 40 GbE would
be much appreciated, as I am still unsure what could be causing the issue.

Thanks,

Mark

On Fri, Jun 30, 2017 at 3:57 AM, Paul Prozesky <paul.proze...@gmail.com>
wrote:

> Morning Mark
>
> Please have a look here for SKARAB 40gbe TX and RX models with demo
> software.
>
> https://github.com/ska-sa/mkat_fpga/tree/devel/source/skarab_dev/tut2
>
> Cheers
> Paul
>
>
> On 30 June 2017 at 07:46, Jason Manley <jman...@ska.ac.za> wrote:
>
>> Hi Mark
>>
>> The current SKARAB 40G yellowblock is a bit of a hack.
>>
>>   1) It is currently not parameterised, and is hard-coded for the first
>> port on Mezzanine slot 3.
>>
>>   2) The tx_valid and rx_valid lines are 4-bits wide, not 1 bit. This
>> will be rectified soon, but in the meanwhile, just feed the value "3" to
>> tx_valid to send packets.
>>
>>   3) Note that there was a recent change to the TX and RX 64-bit word
>> ordering (was previously incorrectly swapped). Make you built your
>> bitstreams with a recent git checkout.
>>
>> It's on our todo list to get it properly parameterised and to fix the
>> 4-bit weirdness, but it's not clear when we'll have that done.  In the
>> meanwhile, the 40G does work, and we are successfully using this first port
>> actively at SKA-SA.
>>
>> Some things you should try to help debug:
>>
>>   1) The microblaze will attempt to DHCP on the 40G interface. Did it
>> obtain a lease? Check your DHCP server logs.
>>
>>   2) Check (using casperfpga software) that the cores are actually
>> configured like you think. There was a version of microblaze that overwrote
>> things. And if it's DHCP'ing (this is how we use the ports), then the IP
>> will have changed from what you expect. 
>> myfpgaobject.gbes['my_forty_gbe_core'].print_core_details()
>> (or g.get_core_details()).
>>
>>   3) What does tcpdump/wireshark show is coming out of the TX board?
>>
>>   4) Did you select different MAC addresses for the "hardcoded"
>> yellowblocks on the TX and RX side? Else a switch might not forward the
>> packets.
>>
>>   5) Can you ping both 40G interfaces from a computer?
>>
>> Jason Manley
>> CBF Manager
>> SKA-SA
>>
>> Cell: +27 82 662 7726 <+27%2082%20662%207726>
>> Work: +27 21 506 7300 <+27%2021%20506%207300>
>>
>> On 29 Jun 2017, at 20:37, Peryer, Mark A. <mark.per...@cfa.harvard.edu>
>> wrote:
>>
>> > Hello,
>> >
>> > I am trying to send data from one SKARAB to another SKARAB over 40GbE.
>> I have created two separate JASPER files, one for receiving and one for
>> transmitting. Each design has one forty_gbe yellow block and are configured
>> similar to Tutorial 2 on the casper website. In the JASPER file used for
>> transmitting, I have placed a snapshot block on the tx_data signal for the
>> forty_gbe block and am able to read the correct data from the snapshot
>> block using casperfpga. While it appears that the correct data is being
>> transmitted, nothing is received by the second SKARAB. In the JASPER file
>> used for receiving data, I have a snapshot block on the rx_data signal,
>> which should trigger once a valid frame is received. However, when I run
>> fpga01.snapshots.snapshot2.print_snap(50) it just hangs, indicating
>> nothing has been received.
>> >
>> > I did notice that when I right click on the forty_gbe yellow block and
>> go to Mask >> Edit Mask >> Parameters, there is a menu that allows
>> for the card slot location of the 40GbE card to be selected. Our SKARAB
>> units have the 40GbE card populated on Mezzanine Slot 3, however only Card
>> Slot 0 and 1 are available to be selected. Should this option be set to
>> slot 3 in order to prope

[casper] Configuring 40GbE Yellow Block in JASPER

[Peryer, Mark A.]

Hello,

I am trying to send data from one SKARAB to another SKARAB over 40GbE. I
have created two separate JASPER files, one for receiving and one for
transmitting. Each design has one forty_gbe yellow block and are configured
similar to Tutorial 2 on the casper website. In the JASPER file used for
transmitting, I have placed a snapshot block on the tx_data signal for the
forty_gbe block and am able to read the correct data from the snapshot
block using casperfpga. While it appears that the correct data is being
transmitted, nothing is received by the second SKARAB. In the JASPER file
used for receiving data, I have a snapshot block on the rx_data signal,
which should trigger once a valid frame is received. However, when I run
fpga01.snapshots.snapshot2.print_snap(50) it just hangs, indicating nothing
has been received.

I did notice that when I right click on the forty_gbe yellow block and go
to Mask >> Edit Mask >> Parameters, there is a menu that allows for
the card slot location of the 40GbE card to be selected. Our SKARAB units
have the 40GbE card populated on Mezzanine Slot 3, however only Card Slot 0
and 1 are available to be selected. Should this option be set to slot 3 in
order to properly use the 40GbE ports?

I should also mention that I have configured the tx_dest_ip block input to
be 192.168.5.20 and the tx_dest_port to be 1, which are the default
values for the forty_gbe block.

If there is anything else I should look at in order to properly configure
the forty_gbe yellow blocks please advise.

Thanks,

Mark

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Re: [casper] Uploading Jasper .fpg Files to SKARAB

[Peryer, Mark A.]

In regards to the second question I asked in my previous email, I have
solved the issue of being able to read the software registers and snapshot
blocks. I needed to write the correct values to the software registers
after programming in order to properly initialize the design.

Thanks,

Mark

On Wed, Jun 28, 2017 at 12:33 PM, Peryer, Mark A. <
mark.per...@cfa.harvard.edu> wrote:

> Hello,
>
> There still appears to be an issue with the firmware version loaded onto
> the Virtex 7. As the image below shows, after a power cycle the SKARAB
> boots from the "multi-boot" image. However, once the .fpg file is uploaded,
> the Virtex 7 reverts back to using the toolflow image.
>
> Additionally, I have been having an issue reading the correct values
> stored in software registers and snapshot blocks in my JASPER design. Could
> this be related to booting from the incorrect firmware image, or is it a
> separate issue?
>
>
> [image: Inline image 1]
>
> Thanks,
>
> Mark
>
> On Tue, Jun 27, 2017 at 11:04 AM, Clifford van Dyk <
> cliffordvan...@gmail.com> wrote:
>
>> Excellent! Welcome to Skarab!
>>
>> Kind regards,
>> Clifford
>>
>> On 6/27/2017 3:55 PM, Young, Andre wrote:
>> > Hi Clifford, Adam
>> >
>> > Looks like it was the server NIC MTU size, I changed it from 1500 to
>> > 9000 and then:
>> >
>> > # skarab-01
>> > In [8]:
>> > fpga.upload_to_ram_and_program('realtimeaphids_6_20_2017-6-
>> 22_0944.fpg')
>> > Out[8]: True
>> >
>> > # skarab-02
>> > In [10]:
>> > fpga.upload_to_ram_and_program('realtimeaphids_6_20_2017-6-
>> 22_0944.fpg')
>> > Out[10]: True
>> >
>> > Issue with golden image boot noted, we'll continue to look at that.
>> >
>> > Thanks very much,
>> > André
>> >
>>
>>
>

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Re: [casper] Uploading Jasper .fpg Files to SKARAB

[Peryer, Mark A.]

Hello,

There still appears to be an issue with the firmware version loaded onto
the Virtex 7. As the image below shows, after a power cycle the SKARAB
boots from the "multi-boot" image. However, once the .fpg file is uploaded,
the Virtex 7 reverts back to using the toolflow image.

Additionally, I have been having an issue reading the correct values stored
in software registers and snapshot blocks in my JASPER design. Could this
be related to booting from the incorrect firmware image, or is it a
separate issue?


[image: Inline image 1]

Thanks,

Mark

On Tue, Jun 27, 2017 at 11:04 AM, Clifford van Dyk  wrote:

> Excellent! Welcome to Skarab!
>
> Kind regards,
> Clifford
>
> On 6/27/2017 3:55 PM, Young, Andre wrote:
> > Hi Clifford, Adam
> >
> > Looks like it was the server NIC MTU size, I changed it from 1500 to
> > 9000 and then:
> >
> > # skarab-01
> > In [8]:
> > fpga.upload_to_ram_and_program('realtimeaphids_6_20_2017-6-22_0944.fpg')
> > Out[8]: True
> >
> > # skarab-02
> > In [10]:
> > fpga.upload_to_ram_and_program('realtimeaphids_6_20_2017-6-22_0944.fpg')
> > Out[10]: True
> >
> > Issue with golden image boot noted, we'll continue to look at that.
> >
> > Thanks very much,
> > André
> >
>
>

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Re: [casper] Uploading Jasper .fpg Files to SKARAB

[Peryer, Mark A.]

branch has been selected.


Thanks,

Mark Peryer

On Wed, Jun 21, 2017 at 9:53 AM, Wesley New <wes...@ska.ac.za> wrote:

> Hi Mark,
>
> The jasper_vivado_2016_2 is an older branch that has now been merged into
> Master. There are a lot of changes that have happened subsequent to that in
> master. So please use Master to rebuild the fpg file and try to program
> again.
>
> Ill remove that old branch shortly.
>
> Regards
>
> Wes
>
> Wesley New
> South African SKA Project
> +2721 506 7300 <+27%2021%20506%207300>
> www.ska.ac.za
>
>
>
> On Wed, Jun 21, 2017 at 3:46 PM, Peryer, Mark A. <
> mark.per...@cfa.harvard.edu> wrote:
>
>> Hello,
>>
>> I am currently trying to upload a .fpg file to a SKARAB created with the
>> jasper_vivado_2016_2 branch (commit 6172a4b) of
>> https://github.com/ska-sa/mlib_devel. Using the latest version of
>> casperfpga (commit ec0c355) from the devel branch,
>> https://github.com/ska-sa/casperfpga/tree/devel, I receive the following
>> error.
>>
>>
>> import casperfpga
>> fpga = casperfpga.CasperFpga('skarab-02')
>> fpga.is_connected()
>> True
>> fpga.upload_to_ram_and_program('/home/mark.peryer/realtimeap
>> hids_6_20_2017-6-20_1515.fpg')
>>
>> ERROR:casperfpga.transport_skarab:An older version of mlib_devel
>> generated /home/mark.peryer/realtimeaphids_6_20_2017-6-20_1515.fpg.
>> Please update to include the md5sum on the bitstream in the .fpg header.
>>
>> Any help would be appreciated.
>>
>> Thanks,
>>
>> Mark Peryer
>>
>> --
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>>
>
>

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[casper] Uploading Jasper .fpg Files to SKARAB

[Peryer, Mark A.]

Hello,

I am currently trying to upload a .fpg file to a SKARAB created with the
jasper_vivado_2016_2 branch (commit 6172a4b) of
https://github.com/ska-sa/mlib_devel. Using the latest version of
casperfpga (commit ec0c355) from the devel branch,
https://github.com/ska-sa/casperfpga/tree/devel, I receive the following
error.


import casperfpga
fpga = casperfpga.CasperFpga('skarab-02')
fpga.is_connected()
True
fpga.upload_to_ram_and_program('/home/mark.peryer/realtimeaphids_6_20_2017-6-20_1515.fpg')

ERROR:casperfpga.transport_skarab:An older version of mlib_devel generated
/home/mark.peryer/realtimeaphids_6_20_2017-6-20_1515.fpg. Please update to
include the md5sum on the bitstream in the .fpg header.

Any help would be appreciated.

Thanks,

Mark Peryer

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Re: [casper] Unable to Load Firmware Image onto SKARAB

[Peryer, Mark A.]

...@ska.ac.za>
>> wrote:
>>
>>> Hi Jonathan and Mark,
>>>
>>>
>>> Yes, JTAG is the way. Okay, I have done this before. This is what needs
>>> to be done and I am going via memory here - will confirm when I am in the
>>> office tomorrow:
>>>
>>> 1) Remove the SKARAB lid
>>> 2) This is TBC, but you will need to short the jumper on P9 (schematic
>>> page 42), which will add the Virtex 7 and reconfig device to the JTAG
>>> chain. I know I need to do this when I run the Vivado ILA.
>>> 3)  The JTAG connector is ref des JP3, which is a 20 pin header. You
>>> will need to use the Xilinx USB Platform Programmer Cable to connect to the
>>> 20 pin header using the fly leads that come with the Xilinx USB Platform
>>> Programmer Cable. NB: Remember to install the USB drivers as specified in
>>> the Vivado install How To.
>>> 4) Open Vivado and open the Hardware Manager. First, auto connect and
>>> make sure the FPGA can be detected. Then add the flash device. I used the
>>> "mt28gu01gaax1e-bps-x16" device together with the *.MCS files stored in
>>> the repo. You just need to configure the multi-boot image to gain access to
>>> the board via the 1GbE interface again. Set the RS pins to [25:24]. You may
>>> need the *.prm files, which are available in
>>> https://drive.google.com/drive/folders/0B2dCFqGD5y-8eHlSVlFr
>>> UVdPOVE?usp=sharing. If you do then let me know and I will add them to
>>> the repo.
>>> 5) Configure the flash, verify and then power off the board and see if
>>> the 1GbE comes up.
>>>
>>> If you are still struggling then I will generate a proper How To
>>> document tomorrow with graphics etc. I will probably do that anyway.
>>>
>>> Good luck!
>>>
>>>
>>>
>>> On Wed, Jun 14, 2017 at 11:44 PM, Jonathan Weintroub <
>>> jweintr...@cfa.harvard.edu> wrote:
>>>
>>>> Hi Wes and other SKARAB experts,
>>>>
>>>> To my understanding our SKARAB is now "bricked" and no longer responds
>>>> on Ethernet at all. We now need a way to bring it back to life from a
>>>> straight off the factory floor state.  We surmise this involves JTAG and
>>>> while there is a tantalizing mention of this protocol in the docs Adam
>>>> supplied, there are no details.
>>>>
>>>> We may need Peralex expert support here.  We are time constrained on
>>>> this project and need to get rolling.
>>>>
>>>> Please advise, thanks!
>>>>
>>>> Jonathan Weintroub
>>>> SAO
>>>>
>>>>
>>>> On Wed, Jun 14, 2017 at 5:11 PM Wesley New <wes...@ska.ac.za> wrote:
>>>>
>>>>> Hi Mark,
>>>>>
>>>>> Firstly, welcome to the CASPER community.
>>>>>
>>>>> The SKARAB has multiple images stored in Flash. These are meant only
>>>>> used for the initial FPGA image at start up and a fall back image. This is
>>>>> a Xilinx standard method of configuration. You should be using the
>>>>> upload_to_ram_and_program function. This function uploads the your 
>>>>> compiled
>>>>> fpg file to the SDRAM and then triggers the Virtex to program itself from
>>>>> the SDRAM. You will probably have overwritten the boot images. :(
>>>>>
>>>>> import casperfpgaSKARAB_IP = '10.99.45.170'SKARAB_FPG = 'skarab.fpg'# 
>>>>> skarab programmingskarab = 
>>>>> casperfpga.CasperFpga(SKARAB_IP)skarab.upload_to_ram_and_program(SKARAB_FPG)
>>>>>
>>>>> Does the board come back after waiting some time?
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> Wesley New
>>>>> South African SKA Project
>>>>> +2721 506 7300 <+27%2021%20506%207300>
>>>>> www.ska.ac.za
>>>>>
>>>>>
>>>>>
>>>>> On Wed, Jun 14, 2017 at 7:16 PM, Peryer, Mark A. <
>>>>> mark.per...@cfa.harvard.edu> wrote:
>>>>>
>>>>>> Hello,
>>>>>>
>>>>>> After trying to reconfigure the flash memory on the Virtex7 FPGA with
>>>>>> a new image, I am no longer able to connect to the SKARAB through
>>>>>> casperfpga using the 1GigE port. When I enter the command fpga =
>>>>>> casperfpga.SkarabFp

[casper] Unable to Load Firmware Image onto SKARAB

[Peryer, Mark A.]

Hello,

After trying to reconfigure the flash memory on the Virtex7 FPGA with a new
image, I am no longer able to connect to the SKARAB through casperfpga
using the 1GigE port. When I enter the command fpga =
casperfpga.SkarabFpga('169.254.128.213'), the following is output.

DEBUG:casperfpga.casperfpga:169.254.128.213: now a CasperFpga
DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 0
DEBUG:casperfpga.skarab_fpga:Waiting for response.
DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 1
DEBUG:casperfpga.skarab_fpga:Waiting for response.
DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
DEBUG:casperfpga.skarab_fpga:Retransmit attempts: 2
DEBUG:casperfpga.skarab_fpga:Waiting for response.
DEBUG:casperfpga.skarab_fpga:No packet received: will retransmit
ERROR:casperfpga.skarab_fpga:Socket timeout. Response packet not received.

My thinking is that the firmware image loaded into the flash is corrupt and
now the 1GigE port is disabled. Are these any other possible ways to load a
firmware image into flash without using the 1GigE port, such as the USB
port or JTAG header? If so, what would be the required procedure to do so?

Thanks,

Mark Peryer

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[casper] Uploading JASPER files on SKARAB

[Peryer, Mark A.]

Hello,

I am currently trying to find a way to load the .bof file generated from
JASPER onto a SKARAB. Does a library such as corr, that is used for the
ROACH2, exist for the SKARAB, or is there some other method that needs to
be used?

Thanks,

Mark

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