Re: [casper] katadc

[James Smith]

Hello Heystek,

It's conventional to use the sync0..3 outputs of the KatADC (through an OR
gate) into the Sync input of your PFB. This should be a PPS signal.

Do you have a PPS signal and clock reference going into your katadc? What
speed (i.e. FPGA clock frequency) are you running at? Try doing some
initial debugging e.g. in casperfpga in python with
fpga.estimate_clock_freq() or something like that, I can't remember the
exact name of the function.

It also helps to connect that OR-gated sync signal to a 1-bit counter and
to an LED output so you can actually see if a PPS is getting to the right
place.

Regards,
James


On Wed, May 17, 2017 at 9:57 AM, Heystek Grobler 
wrote:

> Hi James
>
> Physically I have connected the signal generator to the katadc's "i" input
> connector with a square wave at 50MHz with amplitude of 2Vpp.
>
> The simulink model is connected as follows:
>
> [image: Inline image 2]
> If I program the ROACH and pull a spectrum of It I get nothing (only a
> straight line through zero) or sometimes I get the most random noise that
> is all over the place.
>
> Heystek
>
>
>
>
>
>
>
>
>
> On Wed, May 17, 2017 at 9:48 AM, James Smith  wrote:
>
>> Hello Heystek,
>>
>> If you're not getting a spectrum, what are you getting? How have you
>> connected your katadc? (Both physically and with the yellow block)?
>>
>> Regards,
>> James
>>
>>
>> On Wed, May 17, 2017 at 9:46 AM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Good day everyone
>>>
>>> I am trying to implement tutorial 3 on a ROACH1 with a katadc. I have
>>> previously done it on a ROACH2 with the iadc.
>>>
>>> For some reason I am struggling to get the katadc to work. I am using
>>> the katadc yellow block but I cant generate a spectrum. I hooked up an
>>> signal generator to the katadc and gave it a square wave at 50MHz.
>>>
>>> Am I doing something stupid? Or is there another yellow block that I
>>> should rather use.
>>>
>>> Have a great day
>>>
>>> Heystek Grobler
>>>
>>> --
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>>>
>>
>>
>

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Re: [casper] katadc

[Heystek Grobler]

Hi James

Physically I have connected the signal generator to the katadc's "i" input
connector with a square wave at 50MHz with amplitude of 2Vpp.

The simulink model is connected as follows:

[image: Inline image 2]
If I program the ROACH and pull a spectrum of It I get nothing (only a
straight line through zero) or sometimes I get the most random noise that
is all over the place.

Heystek









On Wed, May 17, 2017 at 9:48 AM, James Smith  wrote:

> Hello Heystek,
>
> If you're not getting a spectrum, what are you getting? How have you
> connected your katadc? (Both physically and with the yellow block)?
>
> Regards,
> James
>
>
> On Wed, May 17, 2017 at 9:46 AM, Heystek Grobler  > wrote:
>
>> Good day everyone
>>
>> I am trying to implement tutorial 3 on a ROACH1 with a katadc. I have
>> previously done it on a ROACH2 with the iadc.
>>
>> For some reason I am struggling to get the katadc to work. I am using
>> the katadc yellow block but I cant generate a spectrum. I hooked up an
>> signal generator to the katadc and gave it a square wave at 50MHz.
>>
>> Am I doing something stupid? Or is there another yellow block that I
>> should rather use.
>>
>> Have a great day
>>
>> Heystek Grobler
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "casper@lists.berkeley.edu" group.
>> To unsubscribe from this group and stop receiving emails from it, send an
>> email to casper+unsubscr...@lists.berkeley.edu.
>> To post to this group, send email to casper@lists.berkeley.edu.
>>
>
>

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Re: [casper] katadc

[James Smith]

Hello Heystek,

If you're not getting a spectrum, what are you getting? How have you
connected your katadc? (Both physically and with the yellow block)?

Regards,
James


On Wed, May 17, 2017 at 9:46 AM, Heystek Grobler 
wrote:

> Good day everyone
>
> I am trying to implement tutorial 3 on a ROACH1 with a katadc. I have
> previously done it on a ROACH2 with the iadc.
>
> For some reason I am struggling to get the katadc to work. I am using the
> katadc yellow block but I cant generate a spectrum. I hooked up an signal
> generator to the katadc and gave it a square wave at 50MHz.
>
> Am I doing something stupid? Or is there another yellow block that I
> should rather use.
>
> Have a great day
>
> Heystek Grobler
>
> --
> You received this message because you are subscribed to the Google Groups "
> casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to casper+unsubscr...@lists.berkeley.edu.
> To post to this group, send email to casper@lists.berkeley.edu.
>

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Re: [casper] katadc help in simulink

[James Smith]

Hello Heystek,

It's probably better practice to use software registers (or you could just
use one register for all four inputs and slice it out), but you should also
have been able to use Xilinx constants, that should have compiled.

Regards,
James


On Mon, May 8, 2017 at 3:33 PM, Heystek Grobler 
wrote:

> Hi James
>
> Thanks for the help!! I had to add software registers to en0 and en1 as
> well but know it compiles.
>
> Thanks for the help!!
>
> I really apreciate it
>
> Heystek
>
> On Mon, May 8, 2017 at 2:23 PM, James Smith  wrote:
>
>> Hello Heystek,
>>
>> The KatADC is described here:
>> https://casper.berkeley.edu/wiki/KatADC
>>
>> It's got two channels which you need to enable if you want to use them,
>> and 31.5 dB variable attenuators which you need to set.
>>
>> So if you want them to be on all the time, just hard-wire some 1s into
>> en0 and en1. I'd suggest putting software registers into atten0 and atten1
>> then writing to them from a Python script. You can adjust the attenuation
>> from 0 dB to 31.5 dB in 0.5 dB increments using a 5-bit number.
>>
>> Regards,
>> James
>>
>>
>>
>> On Mon, May 8, 2017 at 2:17 PM, Heystek Grobler > > wrote:
>>
>>> Good day everyone
>>>
>>> I have a ROACH1 board with a katadc. I have located the katadc under the
>>> CAPER XPS Blockset (I am trying to do tut3). I have swapped the iadc for
>>> the katadc.
>>>
>>> The problem is, the katadc has the following inputs:
>>> en0
>>> atten0
>>> en1
>>> atten1
>>>
>>> I need to connect something to those inputs to be able to compile a bof
>>> file. Does anyone perhaps know what inputs I should connect/use?
>>>
>>> Have a great day
>>>
>>> Thanks for the help
>>>
>>> Heystek Grobler
>>>
>>>
>>> --
>>> You received this message because you are subscribed to the Google
>>> Groups "casper@lists.berkeley.edu" group.
>>> To unsubscribe from this group and stop receiving emails from it, send
>>> an email to casper+unsubscr...@lists.berkeley.edu.
>>> To post to this group, send email to casper@lists.berkeley.edu.
>>>
>>
>>
>

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Re: [casper] katadc help in simulink

[Heystek Grobler]

Hi James

Thanks for the help!! I had to add software registers to en0 and en1 as
well but know it compiles.

Thanks for the help!!

I really apreciate it

Heystek

On Mon, May 8, 2017 at 2:23 PM, James Smith  wrote:

> Hello Heystek,
>
> The KatADC is described here:
> https://casper.berkeley.edu/wiki/KatADC
>
> It's got two channels which you need to enable if you want to use them,
> and 31.5 dB variable attenuators which you need to set.
>
> So if you want them to be on all the time, just hard-wire some 1s into en0
> and en1. I'd suggest putting software registers into atten0 and atten1 then
> writing to them from a Python script. You can adjust the attenuation from 0
> dB to 31.5 dB in 0.5 dB increments using a 5-bit number.
>
> Regards,
> James
>
>
>
> On Mon, May 8, 2017 at 2:17 PM, Heystek Grobler 
> wrote:
>
>> Good day everyone
>>
>> I have a ROACH1 board with a katadc. I have located the katadc under the
>> CAPER XPS Blockset (I am trying to do tut3). I have swapped the iadc for
>> the katadc.
>>
>> The problem is, the katadc has the following inputs:
>> en0
>> atten0
>> en1
>> atten1
>>
>> I need to connect something to those inputs to be able to compile a bof
>> file. Does anyone perhaps know what inputs I should connect/use?
>>
>> Have a great day
>>
>> Thanks for the help
>>
>> Heystek Grobler
>>
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "casper@lists.berkeley.edu" group.
>> To unsubscribe from this group and stop receiving emails from it, send an
>> email to casper+unsubscr...@lists.berkeley.edu.
>> To post to this group, send email to casper@lists.berkeley.edu.
>>
>
>

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Re: [casper] katadc help in simulink

[James Smith]

Hello Heystek,

The KatADC is described here:
https://casper.berkeley.edu/wiki/KatADC

It's got two channels which you need to enable if you want to use them, and
31.5 dB variable attenuators which you need to set.

So if you want them to be on all the time, just hard-wire some 1s into en0
and en1. I'd suggest putting software registers into atten0 and atten1 then
writing to them from a Python script. You can adjust the attenuation from 0
dB to 31.5 dB in 0.5 dB increments using a 5-bit number.

Regards,
James



On Mon, May 8, 2017 at 2:17 PM, Heystek Grobler 
wrote:

> Good day everyone
>
> I have a ROACH1 board with a katadc. I have located the katadc under the
> CAPER XPS Blockset (I am trying to do tut3). I have swapped the iadc for
> the katadc.
>
> The problem is, the katadc has the following inputs:
> en0
> atten0
> en1
> atten1
>
> I need to connect something to those inputs to be able to compile a bof
> file. Does anyone perhaps know what inputs I should connect/use?
>
> Have a great day
>
> Thanks for the help
>
> Heystek Grobler
>
>
> --
> You received this message because you are subscribed to the Google Groups "
> casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to casper+unsubscr...@lists.berkeley.edu.
> To post to this group, send email to casper@lists.berkeley.edu.
>

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Re: [casper] KatADC impedance values

[Dan Werthimer]

hi james,

as far as I know,
all the casper adc board inputs are 50 ohms,
except for the differential input version of the adc16 board,
which has 100 ohm differential inputs.

several of the adc boards are not well terminated
(they aren't 50 ohms at all frequencies...),
especially the earlier boards,
so if you want to minimize reflections, I suggest you insert
a 50 ohm attenuator at the input of the ADC.

best wishes,

dan


On Mon, Feb 22, 2016 at 5:17 AM, James Smith  wrote:

> Hi all,
>
> Is there any reason to believe that the input on the KatADC board (or any
> ADC board which we might end up using) is not a 50-ohm? How would one go
> about determining that? The wiki says nothing about its VSWR or related
> information.
>
> Any thoughts would be appreciated.
>
> Regards,
> James
>
>

Re: [casper] KatADC vs ASIAA ADC

[Gopal Narayanan]

Hi Dan

Thanks for your input.

For 800 MHz BW, I am looking for 2048 spectral channels. If that is a tall
order, we could settle for 1024.

I am hoping to double the number of channels for halving the BW. For eg.

BW  NumChannels
8002048
4004096
2008192

I see why you are suggesting the ASIAA dual adc card for the 800 MHz mode.
But I would prefer if we could use the same ADC for all modes. If I were to
use the ASIAA ADC sampling at 1.6 GHz (FPGA clock ~ 200 MHz), and use all 8
parallel streams of the ADC for PFB and FFT then I satisfy that mode. For
the 400 MHz mode, if I leave the sampling clock at 1.6 GHz, but terminate 4
outputs of the 8 parallel streams from the ADC, am I not effectively
sampling at 800 MHz? Can a similar argument not be applied for 400 MHz
sampling? What are the downsides to taking this approach? Am I missing
something obvious?

Cheers,
Gopal




On Thu, Mar 20, 2014 at 3:43 PM, Dan Werthimer d...@ssl.berkeley.eduwrote:


 hi gopal,

 how many spectral channels do you need?

 for 800 MHz bandwidth, you can use a pair of asiaa dual adc's at 2Gsps,
 and get four signal inputs per roach2, and clock the fgpa at 250 MHz. .

 for 400 MHz bandwidth, i suggest you use a pair of adc16 boards
 in quad input mode (sample at 960 Msps, four inputs per board), so
 you can get 8 signal inputs per roach2.   fpga clock of 240 MHz.
 we might have a design for this you can use if you'd like.

 for 200 MHz bandwidth, i suggest you use a pair of adc16 boards
 in octal input mode (sample at 480 Msps, eight inputs per board), so
 you can get 16 signal inputs per roach2.   fpga clock of 240 MHz.

 best wishes,

 dan




 On Thu, Mar 20, 2014 at 10:08 AM, Gopal Narayanan 
 go...@astro.umass.eduwrote:

 Hello Casperites

 I'm looking for advice. We are at the point of launching into a wideband
 spectrometer project for building ROACH-2 based spectrometers to handle 32
 independent front-end inputs. This is a conventional spectrometer (no
 cross-correlations needed). Our maximum bandwidth needed is 800 MHz. We are
 also interested in modes of bandwidth 200 and 400 MHz. I should note that
 legacy IF processors with band-limiting filters for the above BWs already
 exist, and we are building our spectrometer to these bandwidths.

 I am debating between the KatADC board and the wideband ASIAA  5GSPS ADC
 based boards. I ran some preliminary Simulink designs with the KatADC
 boards, and I run into timing issues when I use ADC sampling rate  1200
 MHz. For 1.5 GSPS sampling, the FPGA clock gets up to 375 MHz with the
 KatADC, so perhaps this is the issue. I would like to squeeze 4 pixels into
 one ROACH-2 if possible. Has anyone run the KatADC close to its maximum
 sampling rate with the ROACH-2s? Are plan-ahead and other more advanced
 techniques needed for this?

 Alternatively, we could use the ASIAA ADC board, which has a divided-by-8
 for the FPGA clock from the ADC sample rate. Keeping FPGA clock rates at
 nominal values might be easier with the ASIAA board, especially when we are
 only interested in relatively low sample clocks to 1.6 GHz. We are
 considering the 8-bit DMUX 1:1 version of the ASIAA board.

 Any pointers/advice/suggestions in choosing an appropriate ADC board is
 appreciated!

 Thanks
 Gopal


 --
 Gopal Narayanan  Ph #: (413) 545 0925
 Department of Astronomy  e-mail: go...@astro.umass.edu
 University of Massachusetts  Amherst MA 01003





-- 
Gopal Narayanan  Ph #: (413) 545 0925
Department of Astronomy  e-mail: go...@astro.umass.edu
University of Massachusetts  Amherst MA 01003

Re: [casper] KatADC vs ASIAA ADC

[John Ford]

 John

 We do have switchable analog filters that define the 200, 400 and 800 MHz
 bandpasses in our IF processors. So decimation in sample domain should
 still work.

Yes, that's true.  In our case we want to avoid the complexity of
switching in various bandpass filters for the narrowband case.


 So your point about the relatively slow 200 MHz FPGA speed is that it may
 make more sense to keep the sampling clock a little higher (say 2GHz) so
 that FPGA is at a higher clock rate (250 MHz), and use digital filtering
 (in addition to the defined analog band) to define the bandwidths?

Yes, I think that without tweaking the clock management that you can't run
the FPGA slow enough for 200 MHz /16, and as you say, simply decimating
the output of the ADC ought to work given a reasonable clock rate, like
800 MHz.


 A related question for you. For VEGAS, I thought you were  using
  ADC1x3000-8. Can it go to 3.2 GS/s? Or are you using the ASIAA ADC?

We switched mid-stream to the ASIAA ADC.  It's faster, cheaper, and has
better performance.

John


 Thanks!
 Gopal


 On Fri, Mar 21, 2014 at 1:30 PM, John Ford jf...@nrao.edu wrote:

  Hi Dan
 
  Thanks for your input.
 
  For 800 MHz BW, I am looking for 2048 spectral channels. If that is a
 tall
  order, we could settle for 1024.

 This isn't a problem using roach-2

 
  I am hoping to double the number of channels for halving the BW. For
 eg.
 
  BW  NumChannels
  8002048
  4004096
  2008192

 You can use just one ADC for all of your modes, I think.

 
  I see why you are suggesting the ASIAA dual adc card for the 800 MHz
 mode.
  But I would prefer if we could use the same ADC for all modes. If I
 were
  to
  use the ASIAA ADC sampling at 1.6 GHz (FPGA clock ~ 200 MHz), and use
 all
  8
  parallel streams of the ADC for PFB and FFT then I satisfy that mode.
 For
  the 400 MHz mode, if I leave the sampling clock at 1.6 GHz, but
 terminate
  4
  outputs of the 8 parallel streams from the ADC, am I not effectively
  sampling at 800 MHz? Can a similar argument not be applied for 400 MHz
  sampling? What are the downsides to taking this approach? Am I missing
  something obvious?

 We're looking into doing this, except we may sample faster (at either
 1.6
 GS/s or 3.2 GS/s) and digitally filter down to the other rates to avoid
 having more analog filters in the system.

 You will likely have trouble trying to just scale the sample clock down,
 because at the 200 MHz point, your FPGA will be clocking too slowly.
 Your
 idea of decimating the sample input will probably work well, but you
 will
 have to have analog filters to define the bandpass.

 John

 
  Cheers,
  Gopal
 
 
 
 
  On Thu, Mar 20, 2014 at 3:43 PM, Dan Werthimer
  d...@ssl.berkeley.eduwrote:
 
 
  hi gopal,
 
  how many spectral channels do you need?
 
  for 800 MHz bandwidth, you can use a pair of asiaa dual adc's at
 2Gsps,
  and get four signal inputs per roach2, and clock the fgpa at 250 MHz.
 .
 
  for 400 MHz bandwidth, i suggest you use a pair of adc16 boards
  in quad input mode (sample at 960 Msps, four inputs per board), so
  you can get 8 signal inputs per roach2.   fpga clock of 240 MHz.
  we might have a design for this you can use if you'd like.
 
  for 200 MHz bandwidth, i suggest you use a pair of adc16 boards
  in octal input mode (sample at 480 Msps, eight inputs per board), so
  you can get 16 signal inputs per roach2.   fpga clock of 240 MHz.
 
  best wishes,
 
  dan
 
 
 
 
  On Thu, Mar 20, 2014 at 10:08 AM, Gopal Narayanan
  go...@astro.umass.eduwrote:
 
  Hello Casperites
 
  I'm looking for advice. We are at the point of launching into a
  wideband
  spectrometer project for building ROACH-2 based spectrometers to
 handle
  32
  independent front-end inputs. This is a conventional spectrometer
 (no
  cross-correlations needed). Our maximum bandwidth needed is 800 MHz.
 We
  are
  also interested in modes of bandwidth 200 and 400 MHz. I should note
  that
  legacy IF processors with band-limiting filters for the above BWs
  already
  exist, and we are building our spectrometer to these bandwidths.
 
  I am debating between the KatADC board and the wideband ASIAA  5GSPS
  ADC
  based boards. I ran some preliminary Simulink designs with the
 KatADC
  boards, and I run into timing issues when I use ADC sampling rate 
  1200
  MHz. For 1.5 GSPS sampling, the FPGA clock gets up to 375 MHz with
 the
  KatADC, so perhaps this is the issue. I would like to squeeze 4
 pixels
  into
  one ROACH-2 if possible. Has anyone run the KatADC close to its
 maximum
  sampling rate with the ROACH-2s? Are plan-ahead and other more
 advanced
  techniques needed for this?
 
  Alternatively, we could use the ASIAA ADC board, which has a
  divided-by-8
  for the FPGA clock from the ADC sample rate. Keeping FPGA clock
 rates
  at
  nominal values might be easier with the ASIAA board, especially when
 we
  are
  only interested in relatively low sample clocks to 1.6 GHz. We are
  considering 

Re: [casper] KatADC vs ASIAA ADC

[Gerry Harp]

Hi John

If you can sample 800 MHz bandwidth, then can't you use a digitial 
bandpass filter to get to the lower bandwidths?


Gerry


On 3/21/2014 11:43 AM, John Ford wrote:

John

We do have switchable analog filters that define the 200, 400 and 800 MHz
bandpasses in our IF processors. So decimation in sample domain should
still work.

Yes, that's true.  In our case we want to avoid the complexity of
switching in various bandpass filters for the narrowband case.


So your point about the relatively slow 200 MHz FPGA speed is that it may
make more sense to keep the sampling clock a little higher (say 2GHz) so
that FPGA is at a higher clock rate (250 MHz), and use digital filtering
(in addition to the defined analog band) to define the bandwidths?

Yes, I think that without tweaking the clock management that you can't run
the FPGA slow enough for 200 MHz /16, and as you say, simply decimating
the output of the ADC ought to work given a reasonable clock rate, like
800 MHz.


A related question for you. For VEGAS, I thought you were  using
  ADC1x3000-8. Can it go to 3.2 GS/s? Or are you using the ASIAA ADC?

We switched mid-stream to the ASIAA ADC.  It's faster, cheaper, and has
better performance.

John


Thanks!
Gopal


On Fri, Mar 21, 2014 at 1:30 PM, John Ford jf...@nrao.edu wrote:


Hi Dan

Thanks for your input.

For 800 MHz BW, I am looking for 2048 spectral channels. If that is a

tall

order, we could settle for 1024.

This isn't a problem using roach-2


I am hoping to double the number of channels for halving the BW. For

eg.

BW  NumChannels
8002048
4004096
2008192

You can use just one ADC for all of your modes, I think.


I see why you are suggesting the ASIAA dual adc card for the 800 MHz

mode.

But I would prefer if we could use the same ADC for all modes. If I

were

to
use the ASIAA ADC sampling at 1.6 GHz (FPGA clock ~ 200 MHz), and use

all

8
parallel streams of the ADC for PFB and FFT then I satisfy that mode.

For

the 400 MHz mode, if I leave the sampling clock at 1.6 GHz, but

terminate

4
outputs of the 8 parallel streams from the ADC, am I not effectively
sampling at 800 MHz? Can a similar argument not be applied for 400 MHz
sampling? What are the downsides to taking this approach? Am I missing
something obvious?

We're looking into doing this, except we may sample faster (at either
1.6
GS/s or 3.2 GS/s) and digitally filter down to the other rates to avoid
having more analog filters in the system.

You will likely have trouble trying to just scale the sample clock down,
because at the 200 MHz point, your FPGA will be clocking too slowly.
Your
idea of decimating the sample input will probably work well, but you
will
have to have analog filters to define the bandpass.

John


Cheers,
Gopal




On Thu, Mar 20, 2014 at 3:43 PM, Dan Werthimer
d...@ssl.berkeley.eduwrote:


hi gopal,

how many spectral channels do you need?

for 800 MHz bandwidth, you can use a pair of asiaa dual adc's at

2Gsps,

and get four signal inputs per roach2, and clock the fgpa at 250 MHz.

.

for 400 MHz bandwidth, i suggest you use a pair of adc16 boards
in quad input mode (sample at 960 Msps, four inputs per board), so
you can get 8 signal inputs per roach2.   fpga clock of 240 MHz.
we might have a design for this you can use if you'd like.

for 200 MHz bandwidth, i suggest you use a pair of adc16 boards
in octal input mode (sample at 480 Msps, eight inputs per board), so
you can get 16 signal inputs per roach2.   fpga clock of 240 MHz.

best wishes,

dan




On Thu, Mar 20, 2014 at 10:08 AM, Gopal Narayanan
go...@astro.umass.eduwrote:


Hello Casperites

I'm looking for advice. We are at the point of launching into a
wideband
spectrometer project for building ROACH-2 based spectrometers to

handle

32
independent front-end inputs. This is a conventional spectrometer

(no

cross-correlations needed). Our maximum bandwidth needed is 800 MHz.

We

are
also interested in modes of bandwidth 200 and 400 MHz. I should note
that
legacy IF processors with band-limiting filters for the above BWs
already
exist, and we are building our spectrometer to these bandwidths.

I am debating between the KatADC board and the wideband ASIAA  5GSPS
ADC
based boards. I ran some preliminary Simulink designs with the

KatADC

boards, and I run into timing issues when I use ADC sampling rate 
1200
MHz. For 1.5 GSPS sampling, the FPGA clock gets up to 375 MHz with

the

KatADC, so perhaps this is the issue. I would like to squeeze 4

pixels

into
one ROACH-2 if possible. Has anyone run the KatADC close to its

maximum

sampling rate with the ROACH-2s? Are plan-ahead and other more

advanced

techniques needed for this?

Alternatively, we could use the ASIAA ADC board, which has a
divided-by-8
for the FPGA clock from the ADC sample rate. Keeping FPGA clock

rates

at
nominal values might be easier with the ASIAA board, especially when

we

are
only interested in relatively low sample clocks to 1.6 GHz. We are

Re: [casper] KatADC vs ASIAA ADC

[Dan Werthimer]

hi gopal,

how many spectral channels do you need?

for 800 MHz bandwidth, you can use a pair of asiaa dual adc's at 2Gsps,
and get four signal inputs per roach2, and clock the fgpa at 250 MHz. .

for 400 MHz bandwidth, i suggest you use a pair of adc16 boards
in quad input mode (sample at 960 Msps, four inputs per board), so
you can get 8 signal inputs per roach2.   fpga clock of 240 MHz.
we might have a design for this you can use if you'd like.

for 200 MHz bandwidth, i suggest you use a pair of adc16 boards
in octal input mode (sample at 480 Msps, eight inputs per board), so
you can get 16 signal inputs per roach2.   fpga clock of 240 MHz.

best wishes,

dan




On Thu, Mar 20, 2014 at 10:08 AM, Gopal Narayanan go...@astro.umass.eduwrote:

 Hello Casperites

 I'm looking for advice. We are at the point of launching into a wideband
 spectrometer project for building ROACH-2 based spectrometers to handle 32
 independent front-end inputs. This is a conventional spectrometer (no
 cross-correlations needed). Our maximum bandwidth needed is 800 MHz. We are
 also interested in modes of bandwidth 200 and 400 MHz. I should note that
 legacy IF processors with band-limiting filters for the above BWs already
 exist, and we are building our spectrometer to these bandwidths.

 I am debating between the KatADC board and the wideband ASIAA  5GSPS ADC
 based boards. I ran some preliminary Simulink designs with the KatADC
 boards, and I run into timing issues when I use ADC sampling rate  1200
 MHz. For 1.5 GSPS sampling, the FPGA clock gets up to 375 MHz with the
 KatADC, so perhaps this is the issue. I would like to squeeze 4 pixels into
 one ROACH-2 if possible. Has anyone run the KatADC close to its maximum
 sampling rate with the ROACH-2s? Are plan-ahead and other more advanced
 techniques needed for this?

 Alternatively, we could use the ASIAA ADC board, which has a divided-by-8
 for the FPGA clock from the ADC sample rate. Keeping FPGA clock rates at
 nominal values might be easier with the ASIAA board, especially when we are
 only interested in relatively low sample clocks to 1.6 GHz. We are
 considering the 8-bit DMUX 1:1 version of the ASIAA board.

 Any pointers/advice/suggestions in choosing an appropriate ADC board is
 appreciated!

 Thanks
 Gopal


 --
 Gopal Narayanan  Ph #: (413) 545 0925
 Department of Astronomy  e-mail: go...@astro.umass.edu
 University of Massachusetts  Amherst MA 01003

Re: [casper] KATADC attenuators

[Francois Kapp]

Hi Tom,

Not sure if you have resolved this, but there is no jumper setting to
override the attenuation on the KatADC.  There are jumpers (J2, 3) that
force the input switches (U30, 31) on for test purposes.

-F


On Thu, Dec 20, 2012 at 10:57 PM, Tom Kuiper kui...@jpl.nasa.gov wrote:

 I have two KATADCs, one each in ZDOC0 of two ROACH-1 boards (named roach1
 and roach2).  It appears that the attenuator for input 0 of the KATADC in
 roach2 is at 0 dB for whatever attenuation setting command is sent to it.
  The other three inputs respond as I expect.  I assume that this is some
 kind of hardware failure but I thought I'd better check if there was some
 jumper setting or control bit that I don't know about.

 With thanks and best regards,

 Tom




-- 
Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

Team founder: Team SKA Africa
http://www.facebook.com/Team.SKA.Africa
http://teamskaafrica.wordpress.com/
http://www.givengain.com/activist/87536/projects/3987/

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] KATADC gain control

[Tom Kuiper]

On 12/28/2012 08:24 PM, Ryan Monroe wrote:


Hey Tom, remember that the gain setting on the katadc block was not 
enabled on that design.  You'll probably need that to control adc gain


I'd forgotten that you told me that, Ryan, but now that you remind me I 
also recall thinking that since the iic_adc0 register is in the design, 
there must be a way of talking to the KATADC.  That appeared to be the 
case, until I cycled power.  Mason's explanation seems to say that there 
is some other thing that I can do via that register to enable attenuator 
control after power-up.


On 12/28/2012 10:03 PM, Jason Manley wrote:

If you take a look at the KATADC yellow block, you'll see there's an input port for configuring 
it from the simulink gateware. In this spectrometer design, that port is tied to a software 
register called adc_ctrl0. It has 6 bits (lsbs) to set the attenuator in half-db 
steps and the msb toggles the termination switch. So that's what 
self.fpga.write_int('adc_ctrl0',(1  31) + int((20-gain)*2)) is doing. This was done to 
remain compatible with the iadc design of the same spectrometer, where we use external 
minicircuits attenuators and switches and control them using the same software register (from 
which the FPGA serialises this on GPIO pins).
   

Thanks.  That's what I suspected from the
if self.adc_type == 'katadc':
...
elif self.adc_type == 'iadc':
...
test in spec.rf_gain_set() since the IADC doesn't have an RF stage.  I 
thought that maybe there was something KATADC-specific elsewhere in the 
code.

The ADC will retain this setting (even with FPGA reprogramming) unless it is 
explicitly reconfigured from software or by the FPGA's onboard controller or is 
reset by power cycling. By default, such a controller is compiled-in when you 
compile for the KATADC.

I am out of the office, but will happily check the I2C controller when I get 
back in January. I last checked this on ROACH-1 in ~2011 and don't think it's 
ever been tested on ROACH-2. Perhaps something's gone awry with the base 
packages.
   
Well, we are using ROACH-1s and I should have made that explicit.  
Apologies.  I guess, pending a resolution of this issue, I can try a 
work-around in which I first load KAT_rfi_sys and then replace it with 
kurtspec.  Not elegant but ...


Thanks and Happy New Year to all

Tom

Jason

On 29 Dec 2012, at 05:03, Tom Kuiper wrote:

   

I have two designs I'm playing with.  I find that if I run the KAT_rfi_sys 16K 
spectrometer, then after that I can control the RF attenuators with 
corr.katadc.rf_fe_set().  However, if I load another design developed here 
(kurtspec) into a cold ROACH (i.e. after power cycling) corr.katadc.rf_fe_set() 
doesn't work.

corr.katadc.rf_fe_set() uses corr.katadc.iic_write_register() like this:
iic_write_register(fpga, katadc_n, 0x20+pol, 2, 
0x40+(enabled7)+int((gain*2)+23))
and this iic_write_register() does a series of FPGA register writes:
iic_controller='iic_adc%i' % katadc_n
fpga.blindwrite(iic_controller, '%c%c%c%c' % (0x0,0x00,0x00,0x01), offset=12)
fpga.blindwrite(iic_controller, '%c%c%c%c' % (0x0,0x00, WR | START | LOCK, 
(dev_addr  1) | IIC_WR), offset=0x0)
fpga.blindwrite(iic_controller, '%c%c%c%c' % (0x0,0x00, WR | LOCK, reg_addr), 
offset=0x0)
fpga.blindwrite(iic_controller, '%c%c%c%c' % (0x0,0x00, WR | STOP, reg_value), 
offset=0x0)
fpga.blindwrite(iic_controller, struct.pack('4B',0,0,0,0), offset=12)
That is, it writes to register 'iic_adc0'.

However, I noticed that the KAT_rfi_sys 16K spectrometer initialization script, 
which optimizes the attenuator, actually writes to directly to another FPGA 
register like this:
self.fpga.write_int('adc_ctrl0',(1  31) + int((20-gain)*2))
This makes me think that there is something else going on in the 16K 
spectrometer design that enables gain control and that this stays that way in 
the hardware even when anotherfirmware design is loaded.

Does anyone have any idea about what's going on here?

Thanks and best wishes for the New Year.

Tom

 
   

Re: [casper] KATADC gain control

[Tom Kuiper]

On 12/29/2012 09:19 AM, Tom Kuiper wrote:
I guess, pending a resolution of this issue, I can try a work-around 
in which I first load KAT_rfi_sys and then replace it with kurtspec.  
Not elegant but ...

Yup!  That works.

Thanks for the explanation, Jason.

Tom

Re: [casper] KATADC gain control

[Jason Manley]

If you take a look at the KATADC yellow block, you'll see there's an input port 
for configuring it from the simulink gateware. In this spectrometer design, 
that port is tied to a software register called adc_ctrl0. It has 6 bits 
(lsbs) to set the attenuator in half-db steps and the msb toggles the 
termination switch. So that's what self.fpga.write_int('adc_ctrl0',(1  31) + 
int((20-gain)*2)) is doing. This was done to remain compatible with the iadc 
design of the same spectrometer, where we use external minicircuits attenuators 
and switches and control them using the same software register (from which the 
FPGA serialises this on GPIO pins).

The ADC will retain this setting (even with FPGA reprogramming) unless it is 
explicitly reconfigured from software or by the FPGA's onboard controller or is 
reset by power cycling. By default, such a controller is compiled-in when you 
compile for the KATADC.

I am out of the office, but will happily check the I2C controller when I get 
back in January. I last checked this on ROACH-1 in ~2011 and don't think it's 
ever been tested on ROACH-2. Perhaps something's gone awry with the base 
packages.

Jason

On 29 Dec 2012, at 05:03, Tom Kuiper wrote:

 I have two designs I'm playing with.  I find that if I run the KAT_rfi_sys 
 16K spectrometer, then after that I can control the RF attenuators with 
 corr.katadc.rf_fe_set().  However, if I load another design developed here 
 (kurtspec) into a cold ROACH (i.e. after power cycling) 
 corr.katadc.rf_fe_set() doesn't work.
 
 corr.katadc.rf_fe_set() uses corr.katadc.iic_write_register() like this:
 iic_write_register(fpga, katadc_n, 0x20+pol, 2, 
 0x40+(enabled7)+int((gain*2)+23))
 and this iic_write_register() does a series of FPGA register writes:
 iic_controller='iic_adc%i' % katadc_n
 fpga.blindwrite(iic_controller, '%c%c%c%c' % (0x0,0x00,0x00,0x01), offset=12)
 fpga.blindwrite(iic_controller, '%c%c%c%c' % (0x0,0x00, WR | START | LOCK, 
 (dev_addr  1) | IIC_WR), offset=0x0)
 fpga.blindwrite(iic_controller, '%c%c%c%c' % (0x0,0x00, WR | LOCK, reg_addr), 
 offset=0x0)
 fpga.blindwrite(iic_controller, '%c%c%c%c' % (0x0,0x00, WR | STOP, 
 reg_value), offset=0x0)
 fpga.blindwrite(iic_controller, struct.pack('4B',0,0,0,0), offset=12)
 That is, it writes to register 'iic_adc0'.
 
 However, I noticed that the KAT_rfi_sys 16K spectrometer initialization 
 script, which optimizes the attenuator, actually writes to directly to 
 another FPGA register like this:
 self.fpga.write_int('adc_ctrl0',(1  31) + int((20-gain)*2))
 This makes me think that there is something else going on in the 16K 
 spectrometer design that enables gain control and that this stays that way in 
 the hardware even when anotherfirmware design is loaded.
 
 Does anyone have any idea about what's going on here?
 
 Thanks and best wishes for the New Year.
 
 Tom
 

Re: [casper] KATADC attenuators (Tom Kuiper)

[Larry D'Addario]

Tom,

I suggest that you swap the KATADC boards between roach1 and roach2.  Does the 
problem stay with roach2 or does it move with the KATADC board?  Are you running 
exactly the same .bof file on both ROACHes?


--Larry

--
===
Larry R. D'Addario
Tracking Systems and Applications Section (335)
Jet Propulsion Laboratory, operated by Caltech for NASA

Mail:  M/S 238-333
   4800 Oak Grove Drive
   Pasadena, CA 91109, USA
email: ldadda...@jpl.nasa.gov
phone: +1/818/393-0389   (home 626/351-9357)
fax:   +1/818/393-2488
===

Re: [casper] KATADC attenuators (Tom Kuiper)

[Tom Kuiper]

On 12/20/2012 01:33 PM, Larry D'Addario wrote:
I suggest that you swap the KATADC boards between roach1 and roach2.  
Does the problem stay with roach2 or does it move with the KATADC board?
I'm pretty sure that I know how that would turn out.  Unfortunately, I'm 
at home in West LA, 30 min with no traffic.  I can ask Dong to do it but 
it's a hassle so I'll wait to make sure that I haven't missed some minor 
point.

  Are you running exactly the same .bof file on both ROACHes?

Yes.

Tom

Re: [casper] KatADC counts to volts

[Matt Dexter]

something seems strange.  isn't the input range of the ADC IC :
Vin FSR pin14 low  .590 to .730 Vpp
Vin FSR pin15 high .800 to .940 Vpp
page 11 of 46 of http://www.ti.com/lit/gpn/adc08d1520

I see +/-50 mV  but thats for the common mode input.

On Thu, 9 Aug 2012, Tom Kuiper wrote:

The KatADC is based on the Texas Instruments ADC08D1520. It is an 8-bit 
(255-level) ADC operating between +/- 50 mV (0.392 mV/step). The KatADC has a 
20 dB amplifier (factor of 10 voltage gain).  So this gives it an input range 
of +/- 5 mV, or 0.0392 mV/step (39.2 uV/step).  In the KAT RFI 16K 
spectrometer code I see a count to mV scale factor of 3.93.  I'm missing 
something.  Can anyone set me straight?


Thanks

Tom

--
I or me? http://www.oxforddictionaries.com/page/145

Re: [casper] KatADC documentation and questions

[Nimish Sane]

Thanks Andrew and Francois!

This is a very useful information.

Nimish

On Mon, Mar 19, 2012 at 2:36 AM, Francois Kapp francois.k...@ska.ac.zawrote:

 I just looked through the attenuator data sheet - there are no settling
 time specifications, but I'm sure whatever it is, it will be dominated by
 the time taken to set up the registers.

 -Francois


 On Mon, Mar 19, 2012 at 9:05 AM, Andrew Martens and...@ska.ac.za wrote:

 Hi Nimish

  To be more specific, we would like to change the attenuation in the
  KatADC RF front end every 20 ms and we can allow up to 1 ms of dead
  time/settling time. Do you think this can work?

 Just had a quick look through the IIC controller. Seems to need to write
 around 12 words, each 8 bits in size, using a 100kHz clock. This equates
 to around (10us * 12 * 8) ~= 1ms to change attenuation values so 20ms
 should be enough. I am not sure about the settling time of the
 programmable attenuator.

  A related question is how to change this attenuation. I tried using a
  software register connected to atten* inputs of the KatADC yellow
  block, but the design would not compile. I have not got time to check
  at what stage it fails, but I can look into that. I got the design
  compiled by connecting just the constant blocks to these inputs. Is
  it first of all allowed to have a software register there? If not,
  what would be the way to change this attenuation dynamically?
 
 We have software registers that control this value in designs here. If
 software registers work in other parts of your design, they should work
 here - there is nothing special about those ports. You can also set
 these values in software from the PPC if that is easier, the IIC
 controller can be accessed from the PPC.

 Regards
 Andrew





 --
 Francois Kapp

 Sub-system Manager
 Digital Back End
 meerKAT

 SKA South Africa
 Third Floor
 The Park
 Park Road (off Alexandra Road)
 Pinelands
 7405
 Western Cape
 South Africa

 Latitude: -33.94329 (South); Longitude: 18.48945 (East).

 (p) +27 (0)21 506 7300
 (p) +27 (0)21 506 7360 (direct)
 (f) +27 (0)21 506 7375
 (m) +27 (0)82 787 8407

Re: [casper] KatADC documentation and questions

[Nimish Sane]

Hi Andrew,

Thanks for this information.

To be more specific, we would like to change the attenuation in the KatADC
RF front end every 20 ms and we can allow up to 1 ms of dead time/settling
time. Do you think this can work?

A related question is how to change this attenuation. I tried using a
software register connected to atten* inputs of the KatADC yellow block,
but the design would not compile. I have not got time to check at what
stage it fails, but I can look into that. I got the design compiled by
connecting just the constant blocks to these inputs. Is it first of all
allowed to have a software register there? If not, what would be the way to
change this attenuation dynamically?

Thanks,

Nimish

On Thu, Mar 8, 2012 at 11:22 PM, Andrew Martens and...@ska.ac.za wrote:

 Hi Nimish


  Assuming we have a software register connected to the KatADC atten0
  input, how often/fast can we change the attenuation?
 
 The change in value triggers an IIC operation using a controller in the
 katADC yellow block. The rate at which you can change the
 attenuatation/enable is thus probably on the order of kHz. It was not
 designed to be switched rapidly. If you need more detail I could look in
 the controller.

 Regards
 Andrew

Re: [casper] KatADC documentation and questions

[Nimish Sane]

Hi Andrew,

Thanks for the detailed information.

Assuming we have a software register connected to the KatADC atten0 input,
how often/fast can we change the attenuation?

Thanks,

Nimish

On Thu, Mar 8, 2012 at 1:03 PM, Andrew Martens and...@ska.ac.za wrote:

 Hi Nimish

 The katADC is a bit different from the iADC in that it has some RF
 components before the ADC.

 The input to the ADC can be terminated to 50Ohms via an RF switch. The
 en0 and en1 control this (pulling this low terminates the input).

 There is a fixed 20dB amplifier before each ADC input.

 There is a programmable attenuator in front of each ADC input. The
 attenuation is programmable from 0 dB to 31.5 dB in 0.5 dB steps.
 atten0 and atten1 control this for each ADC (5 integer bits and 1
 fractional bit).

 The katADC is tuned to toggle 3 or 4 bits with an input of -27dBm and 0
 dB total gain. Because of the 20dB amplifier, care should be taken.

 The way things are set up in the yellow block (take a look under the
 mask if interested) is that, directly after ADC configuration, whatever
 configuration is specified on these ports is loaded. This allows a
 setting to be static, or configurable via a software register. Any
 change on these ports causes the new configuration to be loaded
 automatically.

 The yellow block does not simulate the action of the RF switch,
 amplifier or attenuator.

 Regards
 Andrew

 On Thu, 2012-03-08 at 11:24 -0500, Nimish Sane wrote:
  Hi all,
 
 
  Is there any documentation/memo on how to use the KatADC yellow block.
  In particular, I need to know how to use the variable attenuation
  feature (inputs atten*, en*). The documentation here —
  https://casper.berkeley.edu/wiki/KatADC — mentions about a 20dB Gain
  Block (50.0MHz - 850.0MHz), and 0dB to 31.5dB Variable Attenuator
  (controllable in 0.5dB steps). It would be nice to know if someone has
  already figured out how to do it.
 
 
  I believe there is no KatADC tutorial. Does anyone have a model file
  that he/she can share?
 
 
  Also, what should be the power level of the analog signal into the
  KatADC?
 
 
  Thanks,
 
 
  Nimish

Re: [casper] KatADC documentation and questions

[Andrew Martens]

Hi Nimish


 Assuming we have a software register connected to the KatADC atten0
 input, how often/fast can we change the attenuation?
 
The change in value triggers an IIC operation using a controller in the
katADC yellow block. The rate at which you can change the
attenuatation/enable is thus probably on the order of kHz. It was not
designed to be switched rapidly. If you need more detail I could look in
the controller.

Regards
Andrew
 

Re: [casper] KatADC

[Matt Dexter]

Thanks Etienne.


On Wed, 29 Feb 2012, Etienne Bauermeister wrote:


Hi Matt,

The 2/4 Gsps version of the KatADC is based on an engineering sample they 
gave us of a future 2/4 Gsps ADC that is based on the current 1.5/3 Gsps ADC 
- I think it is just an up-sampled version of the latter.  The indication 
from them was that this will be a future product that would be available in a 
few months, but shortly thereafter Texas Instrument bought out National 
Semiconductor and all future ADC development seemed to be put on hold while 
they reorganized.  Subsequently I was informed that if there is a need for 
the part we must ask for it from our local suppliers.  The bottom line is 
that if enough people ask for it then it might become available, otherwise I 
won't bank on it becoming a standard product anytime soon.The bottom line is 
that if enough people ask for it then it might become available, otherwise I 
won't bank on it becoming a standard product anytime soon as other future ADC 
products that they indicated to us would be available has been put on hold as 
well (indefinitely).


Regards
Etienne

On 2/29/2012 9:04 AM, Francois Kapp wrote:

Hi Matt,

As far as we know the part has not been released commercially.  I
suspect if it has not happened by now, it is unlikely to happen.

Regards,
Francois

On Wed, Feb 29, 2012 at 5:11 AM, Matt Dexter
mdex...@calmail.berkeley.edu mailto:mdex...@calmail.berkeley.edu wrote:

Hi all,

Is there any news w/ regard to the  4 GSPS version of the
KatADC using the uptested Natl Semi S7002396 ADC IC ?

Are people using them with Roach2 or other hosts ?
Cost ?

Thanks,
Matt

On Wed, 1 Jun 2011, Dan Werthimer wrote:



hi tom,


regarding pushing the KatADC from 2*1.5 Gsps to 4 Gsps:

it will be difficult, perhaps impossible, to
move 4 Gsps 8 bit ADC data through a single zdoc connector
into roach I.  each of the 32 bit lvds lanes would
have to operate at 1 Gbit/sec, and we've never
tried that on Roach I.the most we've achieved
is 750 Gbit/sec per LVDS pair (using the 3 Gsps ADC board).

we've interleaved a pair of these 3 Gsps ADC's to
get 6 Gsps, using both ZDOC connectors on roach I.

on roach II, it should be possible to input 1Gb/sec
on each LVDS pair (you'd probably want to clock the FPGA
at 500 MHz and use DDR inputs), and then you
could get a 4 Gsps 8 bit ADC on each ZDOC connector.

best wishes,

dan






On 06/01/2011 12:11 PM, Francois Kapp wrote:

Hi Tom,

The 4GSPS version of KatADC is based on an up-tested
version of the
ADC08D1520, which is designated S7002396.  It is unclear
whether this
will be released as a commercial product by National - a few
inquiries
to them couldn't hurt the cause.  So far we have only
received the
one.  The rest of the board is the same as the wide-band
front-end
KatADC version, which is the standard version that Mo builds
(i.e.
with BOM:

http://casper.berkeley.edu/__wiki/images/7/71/KATADC1.3BOM___HF_Build.pdf

http://casper.berkeley.edu/wiki/images/7/71/KATADC1.3BOM_HF_Build.pdf).

If you can extract a chip from National it should be a
simple matter
to get one built.

Regards,
Francois

On Wed, Jun 1, 2011 at 8:26 PM, Tom
Kuiperkui...@jpl.nasa.gov mailto:kui...@jpl.nasa.gov 
wrote:


On 06/01/2011 11:19 AM, John Ford wrote:


I'd like to know more about this ADC on the
hardware wiki page under
KatADC:

Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS),
National Semiconductor
ADC08D1520/S7002396 ADC, RF Front-End

However, the KatADC page doesn't seem to have
any information about it.
Can someone direct me to or send me information
about this?


Hi Tom.  The data sheet's linked here:

http://www.national.com/ds/DC/__ADC08D1520.pdf
http://www.national.com/ds/DC/ADC08D1520.pdf


That's the original 3 Gsamp/s version.  I was asking
about the 4 Gsamp/s
version (see the /S7002396?).  This data sheet probably
predates the newer
version.

Cheers

Tom


From

https://casper.berkeley.edu/__wiki/KatADC
https://casper.berkeley.edu/wiki/KatADC

John



Many thanks,

 

Re: [casper] KatADC

[Jonathan Weintroub]

Hi Matt (and maybe Tom who started this thread last June),

Further to Kim's note, we are also using the ASIAA e2v based board on ROACH 2, 
and we have already demonstrated 8 bit 5 GS/s quad interleaved operation on 
ROACH 2.  It has two IF inputs, and can run in a dual channel 2.5 GS/s mode. 
The inputs have about 2 GHz analog bandwidth.

We're still measuring characteristics (passband shape, distortion, dynamic 
range, etc) and are still in the process of qualifying the board for our 
application.These cautionary remarks aside, it would seem to be a 
reasonably close approximation to (and in some respects a super-set of) the 
KAT-ADC.  We have not hit sourcing problems so far with the e2v  EV8AQ160 ADC 
on which it is based, and I have quotes from Digicom to produce it.

Might this board serve your interests too?   Be good to have more CASPERites on 
board.

Jonathan


On Feb 28, 2012, at 11:11 PM, Matt Dexter wrote:

 Thanks Kim.
 
 On Tue, 28 Feb 2012, Kim Guzzino wrote:
 
 Matt,
  ASIAA and I have the 8bit 5Gsps E2v board made by ASIAA running at
 4Gsps into a ZDOK on a ROACH1. Our ROACH1 has the SX95 chip and uses the
 ddr iserdes inputs. the chip is spec'd to run the io's up at 1Gsps and
 seems to work fine at that speed.
  We are characterizing it now and will be running it at 5Gsps into a
 Roach2. So I don't think you should have problems running the KatADC at
 those speeds.
 
 Kim Guzzino
 
 On Tue, 2012-02-28 at 19:11 -0800, Matt Dexter wrote:
 Hi all,
 
 Is there any news w/ regard to the  4 GSPS version of the
 KatADC using the uptested Natl Semi S7002396 ADC IC ?
 
 Are people using them with Roach2 or other hosts ?
 Cost ?
 
 Thanks,
 Matt
 
 On Wed, 1 Jun 2011, Dan Werthimer wrote:
 
 
 
 hi tom,
 
 
 regarding pushing the KatADC from 2*1.5 Gsps to 4 Gsps:
 
 it will be difficult, perhaps impossible, to
 move 4 Gsps 8 bit ADC data through a single zdoc connector
 into roach I.  each of the 32 bit lvds lanes would
 have to operate at 1 Gbit/sec, and we've never
 tried that on Roach I.the most we've achieved
 is 750 Gbit/sec per LVDS pair (using the 3 Gsps ADC board).
 
 we've interleaved a pair of these 3 Gsps ADC's to
 get 6 Gsps, using both ZDOC connectors on roach I.
 
 on roach II, it should be possible to input 1Gb/sec
 on each LVDS pair (you'd probably want to clock the FPGA
 at 500 MHz and use DDR inputs), and then you
 could get a 4 Gsps 8 bit ADC on each ZDOC connector.
 
 best wishes,
 
 dan
 
 
 
 
 
 
 On 06/01/2011 12:11 PM, Francois Kapp wrote:
 Hi Tom,
 
 The 4GSPS version of KatADC is based on an up-tested version of the
 ADC08D1520, which is designated S7002396.  It is unclear whether this
 will be released as a commercial product by National - a few inquiries
 to them couldn't hurt the cause.  So far we have only received the
 one.  The rest of the board is the same as the wide-band front-end
 KatADC version, which is the standard version that Mo builds (i.e.
 with BOM:
 http://casper.berkeley.edu/wiki/images/7/71/KATADC1.3BOM_HF_Build.pdf).
 
 If you can extract a chip from National it should be a simple matter
 to get one built.
 
 Regards,
 Francois
 
 On Wed, Jun 1, 2011 at 8:26 PM, Tom Kuiperkui...@jpl.nasa.gov  wrote:
 On 06/01/2011 11:19 AM, John Ford wrote:
 
 I'd like to know more about this ADC on the hardware wiki page under
 KatADC:
 
 Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS), National Semiconductor
 ADC08D1520/S7002396 ADC, RF Front-End
 
 However, the KatADC page doesn't seem to have any information about it.
 Can someone direct me to or send me information about this?
 
 
 Hi Tom.  The data sheet's linked here:
 
 http://www.national.com/ds/DC/ADC08D1520.pdf
 
 
 That's the original 3 Gsamp/s version.  I was asking about the 4 Gsamp/s
 version (see the /S7002396?).  This data sheet probably predates the 
 newer
 version.
 
 Cheers
 
 Tom
 
 From
 
 https://casper.berkeley.edu/wiki/KatADC
 
 John
 
 
 
 Many thanks,
 
 Tom
 
 --
 I or me? http://www.oxforddictionaries.com/page/145
 
 
 
 
 
 
 
 
 --
 I or me? http://www.oxforddictionaries.com/page/145
 
 
 
 
 
 
 
 
 
 
 
 
 

Re: [casper] KatADC

[Matt Dexter]

Thanks Kim.

On Tue, 28 Feb 2012, Kim Guzzino wrote:


Matt,
  ASIAA and I have the 8bit 5Gsps E2v board made by ASIAA running at
4Gsps into a ZDOK on a ROACH1. Our ROACH1 has the SX95 chip and uses the
ddr iserdes inputs. the chip is spec'd to run the io's up at 1Gsps and
seems to work fine at that speed.
  We are characterizing it now and will be running it at 5Gsps into a
Roach2. So I don't think you should have problems running the KatADC at
those speeds.

Kim Guzzino

On Tue, 2012-02-28 at 19:11 -0800, Matt Dexter wrote:

Hi all,

Is there any news w/ regard to the  4 GSPS version of the
KatADC using the uptested Natl Semi S7002396 ADC IC ?

Are people using them with Roach2 or other hosts ?
Cost ?

Thanks,
Matt

On Wed, 1 Jun 2011, Dan Werthimer wrote:




hi tom,


regarding pushing the KatADC from 2*1.5 Gsps to 4 Gsps:

it will be difficult, perhaps impossible, to
move 4 Gsps 8 bit ADC data through a single zdoc connector
into roach I.  each of the 32 bit lvds lanes would
have to operate at 1 Gbit/sec, and we've never
tried that on Roach I.the most we've achieved
is 750 Gbit/sec per LVDS pair (using the 3 Gsps ADC board).

we've interleaved a pair of these 3 Gsps ADC's to
get 6 Gsps, using both ZDOC connectors on roach I.

on roach II, it should be possible to input 1Gb/sec
on each LVDS pair (you'd probably want to clock the FPGA
at 500 MHz and use DDR inputs), and then you
could get a 4 Gsps 8 bit ADC on each ZDOC connector.

best wishes,

dan






On 06/01/2011 12:11 PM, Francois Kapp wrote:

Hi Tom,

The 4GSPS version of KatADC is based on an up-tested version of the
ADC08D1520, which is designated S7002396.  It is unclear whether this
will be released as a commercial product by National - a few inquiries
to them couldn't hurt the cause.  So far we have only received the
one.  The rest of the board is the same as the wide-band front-end
KatADC version, which is the standard version that Mo builds (i.e.
with BOM:
http://casper.berkeley.edu/wiki/images/7/71/KATADC1.3BOM_HF_Build.pdf).

If you can extract a chip from National it should be a simple matter
to get one built.

Regards,
Francois

On Wed, Jun 1, 2011 at 8:26 PM, Tom Kuiperkui...@jpl.nasa.gov  wrote:

On 06/01/2011 11:19 AM, John Ford wrote:


I'd like to know more about this ADC on the hardware wiki page under
KatADC:

Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS), National Semiconductor
ADC08D1520/S7002396 ADC, RF Front-End

However, the KatADC page doesn't seem to have any information about it.
Can someone direct me to or send me information about this?



Hi Tom.  The data sheet's linked here:

http://www.national.com/ds/DC/ADC08D1520.pdf



That's the original 3 Gsamp/s version.  I was asking about the 4 Gsamp/s
version (see the /S7002396?).  This data sheet probably predates the newer
version.

Cheers

Tom


From

https://casper.berkeley.edu/wiki/KatADC

John




Many thanks,

Tom

--
I or me? http://www.oxforddictionaries.com/page/145










--
I or me? http://www.oxforddictionaries.com/page/145

Re: [casper] KatADC

[Matt Dexter]

Thanks Francois.
bummer.

Avnet says no stock; need to quote, 60 unit min order.
I haven't tried to contact Avnet for a quote.

Matt

On Wed, 29 Feb 2012, Francois Kapp wrote:


Hi Matt,
As far as we know the part has not been released commercially.  I suspect if
it has not happened by now, it is unlikely to happen.

Regards,
Francois

On Wed, Feb 29, 2012 at 5:11 AM, Matt Dexter mdex...@calmail.berkeley.edu
wrote:
  Hi all,

  Is there any news w/ regard to the  4 GSPS version of the
  KatADC using the uptested Natl Semi S7002396 ADC IC ?

  Are people using them with Roach2 or other hosts ?
  Cost ?

  Thanks,
  Matt

  On Wed, 1 Jun 2011, Dan Werthimer wrote:



hi tom,


regarding pushing the KatADC from 2*1.5 Gsps to 4
Gsps:

it will be difficult, perhaps impossible, to
move 4 Gsps 8 bit ADC data through a single zdoc
connector
into roach I.  each of the 32 bit lvds lanes would
have to operate at 1 Gbit/sec, and we've never
tried that on Roach I.    the most we've achieved
is 750 Gbit/sec per LVDS pair (using the 3 Gsps ADC
board).

we've interleaved a pair of these 3 Gsps ADC's to
get 6 Gsps, using both ZDOC connectors on roach I.

on roach II, it should be possible to input 1Gb/sec
on each LVDS pair (you'd probably want to clock the
FPGA
at 500 MHz and use DDR inputs), and then you
could get a 4 Gsps 8 bit ADC on each ZDOC connector.

best wishes,

dan






On 06/01/2011 12:11 PM, Francois Kapp wrote:
  Hi Tom,

  The 4GSPS version of KatADC is based on
  an up-tested version of the
  ADC08D1520, which is designated
  S7002396.  It is unclear whether this
  will be released as a commercial product
  by National - a few inquiries
  to them couldn't hurt the cause.  So far
  we have only received the
  one.  The rest of the board is the same
  as the wide-band front-end
  KatADC version, which is the standard
  version that Mo builds (i.e.
  with BOM:
  
http://casper.berkeley.edu/wiki/images/7/71/KATADC1.3BOM_HF_Build.pdf).

  If you can extract a chip from National
  it should be a simple matter
  to get one built.

  Regards,
  Francois

  On Wed, Jun 1, 2011 at 8:26 PM, Tom
  Kuiperkui...@jpl.nasa.gov  wrote:
On 06/01/2011 11:19 AM, John
Ford wrote:

I'd
like
to
know
more
about
this
ADC
on
the
hardware
wiki
page
under
KatADC:

Dual
8-bit
2.0GSPS
(or
Single
8-bit
4.0GSPS),
National
Semiconductor
ADC08D1520/S7002396
ADC,
RF
Front-End

However,
the
KatADC
page
doesn't
seem
to
have
any
information
about
it.
Can
someone
direct
me
to
or
send
me
information
about
   

Re: [casper] KatADC

[Etienne Bauermeister]

Hi Matt,

The 2/4 Gsps version of the KatADC is based on an engineering sample 
they gave us of a future 2/4 Gsps ADC that is based on the current 1.5/3 
Gsps ADC - I think it is just an up-sampled version of the latter.  The 
indication from them was that this will be a future product that would 
be available in a few months, but shortly thereafter Texas Instrument 
bought out National Semiconductor and all future ADC development seemed 
to be put on hold while they reorganized.  Subsequently I was informed 
that if there is a need for the part we must ask for it from our local 
suppliers.  The bottom line is that if enough people ask for it then it 
might become available, otherwise I won't bank on it becoming a standard 
product anytime soon.The bottom line is that if enough people ask for it 
then it might become available, otherwise I won't bank on it becoming a 
standard product anytime soon as other future ADC products that they 
indicated to us would be available has been put on hold as well 
(indefinitely).


Regards
Etienne

On 2/29/2012 9:04 AM, Francois Kapp wrote:

Hi Matt,

As far as we know the part has not been released commercially.  I
suspect if it has not happened by now, it is unlikely to happen.

Regards,
Francois

On Wed, Feb 29, 2012 at 5:11 AM, Matt Dexter
mdex...@calmail.berkeley.edu mailto:mdex...@calmail.berkeley.edu wrote:

Hi all,

Is there any news w/ regard to the  4 GSPS version of the
KatADC using the uptested Natl Semi S7002396 ADC IC ?

Are people using them with Roach2 or other hosts ?
Cost ?

Thanks,
Matt

On Wed, 1 Jun 2011, Dan Werthimer wrote:



hi tom,


regarding pushing the KatADC from 2*1.5 Gsps to 4 Gsps:

it will be difficult, perhaps impossible, to
move 4 Gsps 8 bit ADC data through a single zdoc connector
into roach I.  each of the 32 bit lvds lanes would
have to operate at 1 Gbit/sec, and we've never
tried that on Roach I.the most we've achieved
is 750 Gbit/sec per LVDS pair (using the 3 Gsps ADC board).

we've interleaved a pair of these 3 Gsps ADC's to
get 6 Gsps, using both ZDOC connectors on roach I.

on roach II, it should be possible to input 1Gb/sec
on each LVDS pair (you'd probably want to clock the FPGA
at 500 MHz and use DDR inputs), and then you
could get a 4 Gsps 8 bit ADC on each ZDOC connector.

best wishes,

dan






On 06/01/2011 12:11 PM, Francois Kapp wrote:

Hi Tom,

The 4GSPS version of KatADC is based on an up-tested
version of the
ADC08D1520, which is designated S7002396.  It is unclear
whether this
will be released as a commercial product by National - a few
inquiries
to them couldn't hurt the cause.  So far we have only
received the
one.  The rest of the board is the same as the wide-band
front-end
KatADC version, which is the standard version that Mo builds
(i.e.
with BOM:

http://casper.berkeley.edu/__wiki/images/7/71/KATADC1.3BOM___HF_Build.pdf

http://casper.berkeley.edu/wiki/images/7/71/KATADC1.3BOM_HF_Build.pdf).

If you can extract a chip from National it should be a
simple matter
to get one built.

Regards,
Francois

On Wed, Jun 1, 2011 at 8:26 PM, Tom
Kuiperkui...@jpl.nasa.gov mailto:kui...@jpl.nasa.gov  wrote:

On 06/01/2011 11:19 AM, John Ford wrote:


I'd like to know more about this ADC on the
hardware wiki page under
KatADC:

Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS),
National Semiconductor
ADC08D1520/S7002396 ADC, RF Front-End

However, the KatADC page doesn't seem to have
any information about it.
Can someone direct me to or send me information
about this?


Hi Tom.  The data sheet's linked here:

http://www.national.com/ds/DC/__ADC08D1520.pdf
http://www.national.com/ds/DC/ADC08D1520.pdf


That's the original 3 Gsamp/s version.  I was asking
about the 4 Gsamp/s
version (see the /S7002396?).  This data sheet probably
predates the newer
version.

Cheers

Tom


From

https://casper.berkeley.edu/__wiki/KatADC
https://casper.berkeley.edu/wiki/KatADC

John



Many thanks,

Tom

--
I or 

Re: [casper] KatADC

[John Ford]

 I'd like to know more about this ADC on the hardware wiki page under
 KatADC:

 Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS), National Semiconductor
 ADC08D1520/S7002396 ADC, RF Front-End

 However, the KatADC page doesn't seem to have any information about it.
 Can someone direct me to or send me information about this?

Hi Tom.  The data sheet's linked here:

http://www.national.com/ds/DC/ADC08D1520.pdf

From

https://casper.berkeley.edu/wiki/KatADC

John


 Many thanks,

 Tom

 --
 I or me? http://www.oxforddictionaries.com/page/145

Re: [casper] KatADC

[Tom Kuiper]

On 06/01/2011 11:19 AM, John Ford wrote:

I'd like to know more about this ADC on the hardware wiki page under
KatADC:

Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS), National Semiconductor
ADC08D1520/S7002396 ADC, RF Front-End

However, the KatADC page doesn't seem to have any information about it.
Can someone direct me to or send me information about this?
 

Hi Tom.  The data sheet's linked here:

http://www.national.com/ds/DC/ADC08D1520.pdf
   
That's the original 3 Gsamp/s version.  I was asking about the 4 Gsamp/s 
version (see the /S7002396?).  This data sheet probably predates the 
newer version.


Cheers

Tom


From

https://casper.berkeley.edu/wiki/KatADC

John

   

Many thanks,

Tom

--
I or me? http://www.oxforddictionaries.com/page/145



 


   



--
I or me? http://www.oxforddictionaries.com/page/145

Re: [casper] KatADC

[Francois Kapp]

Hi Tom,

The 4GSPS version of KatADC is based on an up-tested version of the
ADC08D1520, which is designated S7002396.  It is unclear whether this
will be released as a commercial product by National - a few inquiries
to them couldn't hurt the cause.  So far we have only received the
one.  The rest of the board is the same as the wide-band front-end
KatADC version, which is the standard version that Mo builds (i.e.
with BOM: 
http://casper.berkeley.edu/wiki/images/7/71/KATADC1.3BOM_HF_Build.pdf).

If you can extract a chip from National it should be a simple matter
to get one built.

Regards,
Francois

On Wed, Jun 1, 2011 at 8:26 PM, Tom Kuiper kui...@jpl.nasa.gov wrote:
 On 06/01/2011 11:19 AM, John Ford wrote:

 I'd like to know more about this ADC on the hardware wiki page under
 KatADC:

 Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS), National Semiconductor
 ADC08D1520/S7002396 ADC, RF Front-End

 However, the KatADC page doesn't seem to have any information about it.
 Can someone direct me to or send me information about this?


 Hi Tom.  The data sheet's linked here:

 http://www.national.com/ds/DC/ADC08D1520.pdf


 That's the original 3 Gsamp/s version.  I was asking about the 4 Gsamp/s
 version (see the /S7002396?).  This data sheet probably predates the newer
 version.

 Cheers

 Tom

 From

 https://casper.berkeley.edu/wiki/KatADC

 John



 Many thanks,

 Tom

 --
 I or me? http://www.oxforddictionaries.com/page/145








 --
 I or me? http://www.oxforddictionaries.com/page/145







-- 

Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] KatADC

[Dan Werthimer]

hi tom,


regarding pushing the KatADC from 2*1.5 Gsps to 4 Gsps:

it will be difficult, perhaps impossible, to
move 4 Gsps 8 bit ADC data through a single zdoc connector
into roach I.  each of the 32 bit lvds lanes would
have to operate at 1 Gbit/sec, and we've never
tried that on Roach I.the most we've achieved
is 750 Gbit/sec per LVDS pair (using the 3 Gsps ADC board).

we've interleaved a pair of these 3 Gsps ADC's to
get 6 Gsps, using both ZDOC connectors on roach I.

on roach II, it should be possible to input 1Gb/sec
on each LVDS pair (you'd probably want to clock the FPGA
at 500 MHz and use DDR inputs), and then you
could get a 4 Gsps 8 bit ADC on each ZDOC connector.

best wishes,

dan






On 06/01/2011 12:11 PM, Francois Kapp wrote:

Hi Tom,

The 4GSPS version of KatADC is based on an up-tested version of the
ADC08D1520, which is designated S7002396.  It is unclear whether this
will be released as a commercial product by National - a few inquiries
to them couldn't hurt the cause.  So far we have only received the
one.  The rest of the board is the same as the wide-band front-end
KatADC version, which is the standard version that Mo builds (i.e.
with BOM: 
http://casper.berkeley.edu/wiki/images/7/71/KATADC1.3BOM_HF_Build.pdf).

If you can extract a chip from National it should be a simple matter
to get one built.

Regards,
Francois

On Wed, Jun 1, 2011 at 8:26 PM, Tom Kuiperkui...@jpl.nasa.gov  wrote:

On 06/01/2011 11:19 AM, John Ford wrote:


I'd like to know more about this ADC on the hardware wiki page under
KatADC:

Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS), National Semiconductor
ADC08D1520/S7002396 ADC, RF Front-End

However, the KatADC page doesn't seem to have any information about it.
Can someone direct me to or send me information about this?



Hi Tom.  The data sheet's linked here:

http://www.national.com/ds/DC/ADC08D1520.pdf



That's the original 3 Gsamp/s version.  I was asking about the 4 Gsamp/s
version (see the /S7002396?).  This data sheet probably predates the newer
version.

Cheers

Tom


From

https://casper.berkeley.edu/wiki/KatADC

John




Many thanks,

Tom

--
I or me? http://www.oxforddictionaries.com/page/145










--
I or me? http://www.oxforddictionaries.com/page/145

Re: [casper] katADC, ISE/SysGen10.1 compatible?

[Jason Manley]

Hi LuisDavid George (as the author of the "yellow block" and underlying controller) is probably the correct person to respond to this question but if you areplanning on switching to the Xilinx 11.x suite, then I would encourage you to do so. We are using 11.5 at KAT and have no problems using the KATADC.FWIW, it looks like ROACH2 will start using 12.x tools so it might be a good idea not to fall too far behind the development versions.JasonOn 26 Mar 2011, at 01:41, Luis Quintero wrote:UPDATE:I created new netlists and verilog files of {fab,cpu}_op_fifo and rx_fifo, using FIFO Generator v4.3 and selecting the options according to theoriginal XCO files.The only thing that I did not copy exactly is the reset_type option of the rx_fifo in v5.3: reset_type=Synchronous_Reset. I am getting this error fromxst:...INSTANCE:iic_adc0...ERROR:HDLCompilers:91 ...\kat_adc_iic_controller_v1_00_a/hdl/verilog/kat_adc_iic_controller.v" line 125 Module 'rx_fifo' does not have a port named 'rst'...The thing is that sync. reset rename the pin to "srst" instead "rst". For testing purposes, I changed this option to async:reset_type=Asynchronous_Reset, and the synthesis finished!! But, is this a safe procedure?I programmed a Roach board, but I am not sure if this trick worked?--In [41]: fpga.progdev('katadc_alone_2011_Mar_25_1844.bof')Out[41]: 'ok'In [36]: corr.katadc.get_ambient_temp(fpga,0)Out[36]: 0.0In [37]: corr.katadc.eeprom_details_get(fpga,0)Out[37]:{'adc_ic_id': 0,'pcb_rev': 0,'reserved': (0, 0, 0, 0),'rf_fe_id': 0,'serial_number': 0}--How can I test if this is working?Thanks again,-- Luis Quintero, Arecibo ObservatoryOn 03/25/2011 04:57 PM, Luis Quintero wrote:Dear katADC users,I am trying to synthesize a simple design using the katadc block (see screen capture in the attachments). This is my tool set in a Windows XP machine:ISE 10.1, SysGen v.10.1.1134, MATLAB R2007b, v7.5.0.342, latest CASPER libs (today's git clone http://casper.berkeley.edu/git/mlib_devel.git).I am getting an exception in xst for iic_adc0:...EXCEPTION:Xdm:FileReader.c:428:$Id: FileReader.c,v 1.36 2004/09/15 20:29:16 jdl Exp $ - Xdm_Exception::UnsupportedFileFormatVersion The Xdm_Model FileFormat version 'V1.5e' is not supportedThe explanation of this issue is available in the Xilinx answers database AR#33915 (http://www.xilinx.com/support/answers/33915.htm). This problem iscaused for version incompatibility of the software that generates some netlist of the CASPER libs and my toolset version.I tried to find all the "iic" things related to katadc in the libs, and generate the netlist using my Xilinx core generator. I started withkat_iic_controller_v1_00_a, I generated the {op,rx}_fifo modules, and I am getting the same exception error from xst.Then I moved to kat_adc_iic_controller_v1_00_a with not success. Apparently the coregen project uses the FIFO generator v5.3, the latest version thatI have is v.4.3.So, my questions are:- Am I seeing the problem in the right way?- Can I generate the netlists of {fab,cpu}_op_fifo and rx_fifo using v4.3 and synthesize the design? If so, can I use the same parameters of the XCOfiles?- Do I have to migrate to ISE/SysGen ver.  11.x? (I planning to do this in the future...)Thanks!-- Luis Quintero, Arecibo Observatory

Re: [casper] katADC, ISE/SysGen10.1 compatible?

[David George]

Hi Luis.

 I created new netlists and verilog files of {fab,cpu}_op_fifo and rx_fifo, 
 using FIFO Generator v4.3 and selecting the options according to the original 
 XCO files.


As you have worked out, the FIFO netlists were generated using ISE 11
tools, making them incompatible with 10.1. Regenerating them as you
did was the right way to go. There shouldn't be any reason that you
cant use the KATADC with 10.1.



 The only thing that I did not copy exactly is the reset_type option of the 
 rx_fifo in v5.3: reset_type=Synchronous_Reset. I am getting this error from 
 xst:


This shouldn't make any difference. Synchronous resets are probably best anyway.


 I programmed a Roach board, but I am not sure if this trick worked?

 --
 In [41]: fpga.progdev('katadc_alone_2011_Mar_25_1844.bof')
 Out[41]: 'ok'

 In [36]: corr.katadc.get_ambient_temp(fpga,0)
 Out[36]: 0.0

 In [37]: corr.katadc.eeprom_details_get(fpga,0)
 Out[37]:
 {'adc_ic_id': 0,
  'pcb_rev': 0,
  'reserved': (0, 0, 0, 0),
  'rf_fe_id': 0,
  'serial_number': 0}
 --


This is definitely not working. I suspect you are getting all zero's
on reads. I'm not really sure why this is happening.

Firstly I would check that PPC comms are okay by reading and writing
to the sys_scratchpad register. I would then dump the
kat_iic_controller register and look for any non-zero values. If you
don't see anything this most likely means something is wrong with the
generated EDK project. Exactly, what would be hard to say. You could
post your generated XPS_ROACH_base/system.mhs and coreinfo.tab  files
which may give some clues.

I think Jason might have some code which manipulates the
kat_iic_controller register directly. This might provide a little more
insight than the corr routines.

Hopefully we can work this one out quickly.

Cheers,
David

Re: [casper] katADC, ISE/SysGen10.1 compatible?

[David George]

Hey Jason (and CASPER)

 FWIW, it looks like ROACH2 will start using 12.x tools so it might be a good
 idea not to fall too far behind the development versions.

ROACH-2 will start out using the 11 toolflow. A whole lot of work is
required to get things moved over to the 12 and 13 tools. We will need
some scheme of migrating from OPB to PLB. That said, we'll get there
eventually.

Cheers,
David

Re: [casper] katADC, ISE/SysGen10.1 compatible?

[Luis Quintero]

UPDATE:

I created new netlists and verilog files of {fab,cpu}_op_fifo and 
rx_fifo, using FIFO Generator v4.3 and selecting the options according 
to the original XCO files.


The only thing that I did not copy exactly is the reset_type option of 
the rx_fifo in v5.3: reset_type=Synchronous_Reset. I am getting this 
error from xst:


...
INSTANCE:iic_adc0...
ERROR:HDLCompilers:91 ...
\kat_adc_iic_controller_v1_00_a/hdl/verilog/kat_adc_iic_controller.v 
line 125 Module 'rx_fifo' does not have a port named 'rst'

...

The thing is that sync. reset rename the pin to srst instead rst. 
For testing purposes, I changed this option to async: 
reset_type=Asynchronous_Reset, and the synthesis finished!! But, is this 
a safe procedure?


I programmed a Roach board, but I am not sure if this trick worked?

--
In [41]: fpga.progdev('katadc_alone_2011_Mar_25_1844.bof')
Out[41]: 'ok'

In [36]: corr.katadc.get_ambient_temp(fpga,0)
Out[36]: 0.0

In [37]: corr.katadc.eeprom_details_get(fpga,0)
Out[37]:
{'adc_ic_id': 0,
 'pcb_rev': 0,
 'reserved': (0, 0, 0, 0),
 'rf_fe_id': 0,
 'serial_number': 0}
--

How can I test if this is working?

Thanks again,

-- Luis Quintero, Arecibo Observatory



On 03/25/2011 04:57 PM, Luis Quintero wrote:

Dear katADC users,

I am trying to synthesize a simple design using the katadc block (see 
screen capture in the attachments). This is my tool set in a Windows 
XP machine: ISE 10.1, SysGen v.10.1.1134, MATLAB R2007b, v7.5.0.342, 
latest CASPER libs (today's git clone 
http://casper.berkeley.edu/git/mlib_devel.git).


I am getting an exception in xst for iic_adc0:

...
EXCEPTION:Xdm:FileReader.c:428:$Id: FileReader.c,v 1.36 2004/09/15 
20:29:16 jdl Exp $ - Xdm_Exception::UnsupportedFileFormatVersion The 
Xdm_Model File Format version 'V1.5e' is not supported.

...


The explanation of this issue is available in the Xilinx answers 
database AR#33915 (http://www.xilinx.com/support/answers/33915.htm). 
This problem is caused for version incompatibility of the software 
that generates some netlist of the CASPER libs and my toolset version.


I tried to find all the iic things related to katadc in the libs, 
and generate the netlist using my Xilinx core generator. I started 
with kat_iic_controller_v1_00_a, I generated the {op,rx}_fifo modules, 
and I am getting the same exception error from xst.


Then I moved to kat_adc_iic_controller_v1_00_a with not success. 
Apparently the coregen project uses the FIFO generator v5.3, the 
latest version that I have is v.4.3.


So, my questions are:
- Am I seeing the problem in the right way?
- Can I generate the netlists of {fab,cpu}_op_fifo and rx_fifo using 
v4.3 and synthesize the design? If so, can I use the same parameters 
of the XCO files?
- Do I have to migrate to ISE/SysGen ver.  11.x? (I planning to do 
this in the future...)


Thanks!

-- Luis Quintero, Arecibo Observatory