On Tue, 2012-04-24 at 23:48 -0500, Ricardo Neri wrote:
On 04/23/2012 08:01 AM, Tomi Valkeinen wrote:
On Wed, 2012-03-28 at 16:38 -0600, Ricardo Neri wrote:
Implement the DSS device driver audio support interface in the HDMI
panel driver and generic driver. The implementation relies on the
On 04/25/2012 05:02 AM, Oleg Matcovschi wrote:
Change-Id: I4ba9de0de4681332539246ccc5e11a7a8fb32e79
Signed-off-by: Oleg Matcovschi oleg.matcovs...@ti.com
---
v1:
initial revision
v2:
resending patch including maintainers
sound/soc/omap/omap-pcm.c |4
1 files changed, 4
On Wed, Apr 25, 2012 at 10:04 AM, DebBarma, Tarun Kanti
tarun.ka...@ti.com wrote:
On Tue, Apr 24, 2012 at 9:34 PM, Tony Lindgren t...@atomide.com wrote:
* DebBarma, Tarun Kanti tarun.ka...@ti.com [120424 08:40]:
Hi Janusz,
On Tue, Apr 24, 2012 at 12:24 AM, DebBarma, Tarun Kanti
From: Govindraj.R govindraj.r...@ti.com
On 24xx/34xx/36xx Module level wakeup events are enabled/disabled using
PM_WKEN1_CORE/PM_WKEN_PER regs.
Add api to control the module level wakeup mechanism from info provided from
hwmod data.
omap_hwmod_enable/disable_wakeup is used from serial.c which
On Tue, 2012-04-24 at 09:35 -0700, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [120420 02:39]:
+
+static int omap4_sar_not_accessible(void)
+{
+ u32 usbhost_state, usbtll_state;
+
+ /*
+* Make sure that USB host and TLL modules are not
+* enabled before
On Tue, 2012-04-24 at 09:39 -0700, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [120420 02:39]:
@@ -384,6 +386,17 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned
int power_state)
set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
if
On Tue, 2012-04-24 at 13:22 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
Transition When CS1 Is Used On EMIF which impacts OMAP443x silicon
On Tue, 2012-04-24 at 12:46 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
This patch adds device off support to OMAP4 device type.
OFF mode is disabled by default, however, there are two ways to enable
OFF mode:
a) In the board file, call
On Wed, Apr 25, 2012 at 05:52:26, Paul Walmsley wrote:
Hello Vaibhav, Afzal, Vaibhav,
A few questions while reviewing this patch:
On Tue, 3 Apr 2012, Vaibhav Hiremath wrote:
AM33XX PRCM module consist of, various clockdomains, in all
total we have 18 clockdomains available, with
On Tue, 2012-04-24 at 12:50 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
The ROM BUG is when MPU Domain OFF wake up sequence that can compromise
IVA and Tesla execution.
At wakeup from MPU OFF on HS
On Tue, 2012-04-24 at 12:57 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
From: Rajendra Nayak rna...@ti.com
On HS devices on the way out of MPU OSWR and OFF ROM code wrongly
overwrites the CM L3INSTR registers. So to avoid this, save them and
restore
On Mon, 2012-04-23 at 11:09 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
[...]
+/**
+ * omap4_dpll_print_reg - dump out a single DPLL register value
+ * @dpll_reg: register to dump
+ * @name: name of the register
+ * @tuple: content of the
Following are a collection of patches that I've need using for a while
to make sure the charge-from-usb on my GTA04 works.
Hopefully I've included the right people in the recipient list :-)
The issues are:
- charge the backup battery as well as the main battery
- charge from a charger which
Signed-off-by: NeilBrown ne...@suse.de
---
drivers/power/twl4030_charger.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/power/twl4030_charger.c b/drivers/power/twl4030_charger.c
index fdad850..3e6e991 100644
--- a/drivers/power/twl4030_charger.c
+++
This allows a voltage and current (bb_uvolts and bb_uamps)
to be specified in the platform_data, and charging of the backup
battery will be enabled with those specification.
As it is not possible to monitor the backup battery at all
there is no new device created to represent it.
Signed-off-by:
We currently refuse to charge if the USB ID pin is grounded, even
though VBUS might be present.
However some chargers do pull the ID pin low through a resistor which
might be as low as 47Kohm (openmoko charger).
The documentation is unclear but some experimental evidence suggests
that when the
The charger needs usb3v1 to be running, so add a new consumer to
keep it running.
This allows the charger to draw current even when the USB driver has
powered down.
Signed-off-by: NeilBrown ne...@suse.de
---
drivers/mfd/twl-core.c |9 +
drivers/power/twl4030_charger.c |
The USB phy is used both for data transfer and to charge the battery.
If the charger it active it will hold a reference to
usb3v1. In that case we don't want to power-down the phy.
This allows charging to continue while the device is suspended.
Signed-off-by: NeilBrown ne...@suse.de
---
Some USB chargers tie the ID pin low via various resistors.
So they can cause VBUS to be high and ID to be low.
The 'A' end of an OTG cable never receives VBUS, it only ever generates it.
So if we see VBUS and are not generating it, this must be a charger,
not the A end of an OTG cable, so in
2012/4/4 Javier Martinez Canillas jav...@dowhile0.org:
board_onenand_init() and board_nand_init() initialization functions are
used to initialize OneNAND and NAND memories respectively. But only
board_nand_init() was visible to be used from board code. This patch makes
possible to initialize a
On Wed, Apr 25, 2012 at 12:56 PM, Tero Kristo t-kri...@ti.com wrote:
On Tue, 2012-04-24 at 13:22 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
2012/4/4 Javier Martinez Canillas jav...@dowhile0.org:
IGEP-based boards can have two different flash memories, a OneNAND or
a NAND device. The boot configuration pins (sys_boot) are used to
specify which memory is available.
Also, this patch removes unnecesary code for registering the
Hi,
On Wed, Apr 25, 2012 at 05:33:11PM +1000, NeilBrown wrote:
Some USB chargers tie the ID pin low via various resistors.
So they can cause VBUS to be high and ID to be low.
The 'A' end of an OTG cable never receives VBUS, it only ever generates it.
this isn't entirely true. Have you
On Tue, Apr 24, 2012 at 07:02:02PM -0700, Oleg Matcovschi wrote:
Change-Id: I4ba9de0de4681332539246ccc5e11a7a8fb32e79
Signed-off-by: Oleg Matcovschi oleg.matcovs...@ti.com
Don't include Change-Ids in upstream submissions, they only make sense
within whatever private development tree you are
Hi Vaibhav,
On 4/25/2012 7:48 AM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 06:33:26, Paul Walmsley wrote:
Hello Vaibhav, Afzal, Vaibhav,
On Tue, 3 Apr 2012, Vaibhav Hiremath wrote:
AM33XX clock implementation is different than any existing OMAP
family of devices. Although DPLL
On Tue, Apr 24, 2012 at 21:50:16, Tony Lindgren wrote:
Thanks Tony for review comments, my response in-lined below -
Hi,
* Vaibhav Hiremath hvaib...@ti.com [120424 02:54]:
Current OMAP code supports couple of clocksource options based
on compilation flag (CONFIG_OMAP_32K_TIMER). The
On Tue, Apr 24, 2012 at 7:53 PM, Kevin Hilman khil...@ti.com wrote:
Iteration over all power domains in the idle path is unnecessary since
only power domains that are transitioning need to be accounted for.
Also PRCM register accesses are known to be expensive, so the
additional latency added
On Wed, 25 Apr 2012, NeilBrown wrote:
Level triggered interrupts do not cause IRQS_PENDING to be set, so
check_wakeup_irqs ignores them.
They don't need to set IRQS_PENDING as the level stays high which
shows that they must be pending. However if such an interrupt fired
during late suspend,
On 04/25/2012 05:02 AM, Oleg Matcovschi wrote:
Change-Id: I4ba9de0de4681332539246ccc5e11a7a8fb32e79
Signed-off-by: Oleg Matcovschi oleg.matcovs...@ti.com
---
v1:
initial revision
v2:
resending patch including maintainers
sound/soc/omap/omap-pcm.c |4
1 files changed, 4
On Wed, 25 Apr 2012 10:50:15 +0200 (CEST) Thomas Gleixner
t...@linutronix.de wrote:
On Wed, 25 Apr 2012, NeilBrown wrote:
Level triggered interrupts do not cause IRQS_PENDING to be set, so
check_wakeup_irqs ignores them.
They don't need to set IRQS_PENDING as the level stays high which
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
Hi Vaibhav,
On 4/25/2012 7:48 AM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 06:33:26, Paul Walmsley wrote:
Hello Vaibhav, Afzal, Vaibhav,
On Tue, 3 Apr 2012, Vaibhav Hiremath wrote:
AM33XX clock implementation is
On Wed, 25 Apr 2012 11:05:27 +0300 Felipe Balbi ba...@ti.com wrote:
Hi,
On Wed, Apr 25, 2012 at 05:33:11PM +1000, NeilBrown wrote:
Some USB chargers tie the ID pin low via various resistors.
So they can cause VBUS to be high and ID to be low.
The 'A' end of an OTG cable never
On Wed, Apr 25, 2012 at 10:33 AM, NeilBrown ne...@suse.de wrote:
Following are a collection of patches that I've need using for a while
to make sure the charge-from-usb on my GTA04 works.
Hopefully I've included the right people in the recipient list :-)
You missed the power supply maintainers
On Wed, Apr 25, 2012 at 10:33 AM, NeilBrown ne...@suse.de wrote:
We currently refuse to charge if the USB ID pin is grounded, even
though VBUS might be present.
However some chargers do pull the ID pin low through a resistor which
might be as low as 47Kohm (openmoko charger).
The
On 4/25/2012 12:20 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
...
That will not change anything, the point is that MODULEMODE_SWCTRL is
uses for module control, not for clock directly, and that's why it is
handled by the hwmod.
That will just
On Wed, Apr 25, 2012 at 10:33 AM, NeilBrown ne...@suse.de wrote:
Some USB chargers tie the ID pin low via various resistors.
So they can cause VBUS to be high and ID to be low.
The 'A' end of an OTG cable never receives VBUS, it only ever generates it.
So if we see VBUS and are not
platform_device pdev can be NULL if CONFIG_MMC_OMAP_HS is not set.
Add check for NULL pointer. while at it move the duplicated functions
to omap4-common.c
Fixes the following boot crash seen with omap4sdp and omap4panda
when MMC is disabled.
Unable to handle kernel NULL pointer dereference at
On Mon, Apr 23, 2012 at 8:13 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Mon, Apr 23, 2012 at 08:11:07PM +0530, Balaji T K wrote:
+int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+ struct omap2_hsmmc_info *c;
+
+ omap_hsmmc_init(controllers);
+ for
I'm running 3.3.0 on an OMAP DM3730, with SMSC75xx connected
via the MUSB device. I get this error continually although
the device (and network channel) seem happy:
musb_ep_program 835: broken !rx_reinit, ep2 csr a200
What does it mean? How do I fix it (i.e. keep it from happening)?
Note:
On Wed, Apr 25, 2012 at 17:08:43, Cousson, Benoit wrote:
On 4/25/2012 12:20 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
...
snip
How would I know the rate of this clock in driver? Say for example, I want
to configure my internal divider based
On Tue, 2012-04-24 at 10:16 -0700, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [120423 00:43]:
Add statics to board-omap4-panda.c's internal functions and data
structures to remove warnings.
Care to update with the warnings produced?
Ah, sure. Updated patch below:
From
On 2012-04-25 06:19, Gary Thomas wrote:
I'm running 3.3.0 on an OMAP DM3730, with SMSC75xx connected
via the MUSB device. I get this error continually although
the device (and network channel) seem happy:
musb_ep_program 835: broken !rx_reinit, ep2 csr a200
What does it mean? How do I fix it
On 4/25/2012 2:26 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 17:08:43, Cousson, Benoit wrote:
On 4/25/2012 12:20 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
...
snip
How would I know the rate of this clock in driver? Say for example, I
On Tue, 2012-04-24 at 00:08 +0300, Grazvydas Ignotas wrote:
VENC output type (composite/svideo) doesn't have to be fixed by board
wiring, it is possible to also provide composite signal through svideo
luminance connector (software enabled), which is what pandora does.
Having to recompile the
On Wed, Apr 25, 2012 at 18:03:21, Cousson, Benoit wrote:
On 4/25/2012 2:26 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 17:08:43, Cousson, Benoit wrote:
On 4/25/2012 12:20 PM, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 14:10:49, Cousson, Benoit wrote:
...
snip
How
On Wed, Apr 25, 2012 at 12:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Wed, Apr 25, 2012 at 10:04 AM, DebBarma, Tarun Kanti
tarun.ka...@ti.com wrote:
On Tue, Apr 24, 2012 at 9:34 PM, Tony Lindgren t...@atomide.com wrote:
* DebBarma, Tarun Kanti tarun.ka...@ti.com [120424
On Wed, 25 Apr 2012, NeilBrown wrote:
On Wed, 25 Apr 2012 10:50:15 +0200 (CEST) Thomas Gleixner
t...@linutronix.de wrote:
On Wed, 25 Apr 2012, NeilBrown wrote:
Level triggered interrupts do not cause IRQS_PENDING to be set, so
check_wakeup_irqs ignores them.
They don't need to
On Tue, Apr 24, 2012 at 7:53 PM, Kevin Hilman khil...@ti.com wrote:
Here's a first pass attempt to reduce the overhead of the pre/post
transitions by allowing them to be called per powerdomain and making
them conditional on powerdomain transtions.
This can be used for testing/measurements to
On Mon, Apr 23, 2012 at 1:13 PM, Ashwin Bihari abih...@gmail.com wrote:
Greetings,
I'm trying to add support for our DM3730-based SOMs to the latest
Kernel and am basing my work on the latest and greatest Linux-next
(3.4.0-rc4-next-20120423-dirty currently) and am finding an
interesting
On Fri, Mar 30, 2012 at 21:33:51, Hiremath, Vaibhav wrote:
After some healthy discussion, now we have come to the conclusion and
decided to handle AM33XX PRM/CM part separately; as AM33XX-PRCM module is
different than OMAP3 and OMAP4 architecture.
The difference becomes very
On Wed, Apr 25, 2012 at 06:24:14PM +0530, DebBarma, Tarun Kanti wrote:
On Wed, Apr 25, 2012 at 12:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Wed, Apr 25, 2012 at 10:04 AM, DebBarma, Tarun Kanti
tarun.ka...@ti.com wrote:
On Tue, Apr 24, 2012 at 9:34 PM, Tony Lindgren
Hi Vaibhav,
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
Thanks for describing it for me. I will change AM33XX clock tree for this
And submit the next version soon.
Well I can just remove those leaf clock entries from my copy here, if
you're okay with that ?
- Paul
--
To unsubscribe from
On Wed, Apr 25, 2012 at 19:25:29, Paul Walmsley wrote:
Hi Vaibhav,
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
Thanks for describing it for me. I will change AM33XX clock tree for this
And submit the next version soon.
Well I can just remove those leaf clock entries from my copy
Current OMAP code supports couple of clocksource options based
on compilation flag (CONFIG_OMAP_32K_TIMER). The 32KHz sync-timer
and a gptimer which can run on 32KHz or system clock (e.g 38.4 MHz)
This patch series cleans up the existing 32k-sync timer implementation
without any major code
Add missing idle_st bit for 32k-sync timer into the prcm-common
header file, required for hwmod data.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Felipe Balbi ba...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Tony Lindgren
Add 32k-sync timer hwmod-data and add ocp_if details to
omap2 3 hwmod table.
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Signed-off-by: Felipe Balbi ba...@ti.com
Reviewed-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc:
Current OMAP code supports couple of clocksource options based
on compilation flag (CONFIG_OMAP_32K_TIMER). The 32KHz sync-timer
and a gptimer which can run on 32KHz or system clock (e.g 38.4 MHz).
So there can be 3 options -
1. 32KHz sync-timer
2. Sys_clock based (e.g 13/19.2/26/38.4 MHz)
On Tue, 2012-04-17 at 10:48 +0200, Ivan Djelic wrote:
This patch adds a simple BCH ecc computation api, similar to the
existing Hamming ecc api. It is intended to be used by the MTD layer.
It implements the following features:
- support 4-bit and 8-bit ecc computation
- do not protect user
Hi Tero,
On 04/25/2012 02:33 AM, Tero Kristo wrote:
On Mon, 2012-04-23 at 11:09 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
[...]
+/**
+ * omap4_dpll_print_reg - dump out a single DPLL register value
+ * @dpll_reg: register to dump
+ * @name: name of
On Tue, 2012-04-17 at 15:49 +0200, Janusz Krzysztofik wrote:
A call to request_mem_region() has been introduced in the omap-gpio
driver recently (commit 96751fcbe5438e95514b025e9cee7a6d38038f40,
gpio/omap: Use devm_ API and add request_mem_region). This change
prevented the Amstrad Delta NAND
Hi Tero,
On 04/25/2012 02:26 AM, Tero Kristo wrote:
On Tue, 2012-04-24 at 13:22 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
Transition When
On 4/25/2012 3:55 PM, Paul Walmsley wrote:
Hi Vaibhav,
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
Thanks for describing it for me. I will change AM33XX clock tree for this
And submit the next version soon.
Well I can just remove those leaf clock entries from my copy here, if
you're okay
Hi,
* Artem Bityutskiy dedeki...@gmail.com [120425 07:52]:
On Tue, 2012-04-17 at 10:48 +0200, Ivan Djelic wrote:
This patch adds a simple BCH ecc computation api, similar to the
existing Hamming ecc api. It is intended to be used by the MTD layer.
It implements the following features:
On Wed, 25 Apr 2012, Cousson, Benoit wrote:
Please take care of changing the hwmod main_clk as well. But maybe
that's not part of that series.
It's not part of the series yet.
Vaibhav, could you take care of changing the main_clk in your hwmod data
patches, and send those to the list?
-
On Wed, Apr 25, 2012 at 21:06:43, Paul Walmsley wrote:
On Wed, 25 Apr 2012, Cousson, Benoit wrote:
Please take care of changing the hwmod main_clk as well. But maybe
that's not part of that series.
It's not part of the series yet.
Vaibhav, could you take care of changing the main_clk
On Wed, 2012-04-25 at 08:23 -0700, Tony Lindgren wrote:
Hi,
* Artem Bityutskiy dedeki...@gmail.com [120425 07:52]:
On Tue, 2012-04-17 at 10:48 +0200, Ivan Djelic wrote:
This patch adds a simple BCH ecc computation api, similar to the
existing Hamming ecc api. It is intended to be used
* Artem Bityutskiy dedeki...@gmail.com [120425 08:48]:
On Wed, 2012-04-25 at 08:23 -0700, Tony Lindgren wrote:
Hi,
* Artem Bityutskiy dedeki...@gmail.com [120425 07:52]:
On Tue, 2012-04-17 at 10:48 +0200, Ivan Djelic wrote:
This patch adds a simple BCH ecc computation api, similar
On Tue, 2012-04-24 at 19:02 -0700, Oleg Matcovschi wrote:
Change-Id: I4ba9de0de4681332539246ccc5e11a7a8fb32e79
Signed-off-by: Oleg Matcovschi oleg.matcovs...@ti.com
---
v1:
initial revision
v2:
resending patch including maintainers
sound/soc/omap/omap-pcm.c |4
1 files
* Afzal Mohammed af...@ti.com [120405 09:06]:
Hi,
GPMC driver conversion series. NAND and smsc911x ethernet device has
been adapted to use GPMC driver.
Patches has been generated over linux-omap/master, HEAD
33fc21e Linux-omap rebuilt: Updated to v3.4-rc1, merged in most of pending
* Afzal Mohammed af...@ti.com [120405 09:08]:
@@ -114,6 +147,8 @@ static struct omap_smsc911x_platform_data smsc911x_cfg = {
static inline void __init omap3evm_init_smsc911x(void)
{
+ struct gpmc_device_pdata *gpmc_smsc911x_info;
+
/* Configure ethernet controller reset gpio
* Tony Lindgren t...@atomide.com [120425 09:01]:
* Artem Bityutskiy dedeki...@gmail.com [120425 08:48]:
On Wed, 2012-04-25 at 08:23 -0700, Tony Lindgren wrote:
Hi,
* Artem Bityutskiy dedeki...@gmail.com [120425 07:52]:
On Tue, 2012-04-17 at 10:48 +0200, Ivan Djelic wrote:
Hi,
Few comments below.
* Ivan Djelic ivan.dje...@parrot.com [120419 11:49]:
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d5108..e3a91a1 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -49,6 +49,7 @@
#define GPMC_ECC_CONTROL
Dnia środa, 25 kwietnia 2012 18:13:38 Artem Bityutskiy pisze:
On Tue, 2012-04-17 at 15:49 +0200, Janusz Krzysztofik wrote:
A call to request_mem_region() has been introduced in the omap-gpio
driver recently (commit 96751fcbe5438e95514b025e9cee7a6d38038f40,
gpio/omap: Use devm_ API and add
Hi Tony,
Thanks for the review,
On Wed, Apr 25, 2012 at 06:03:14PM +0100, Tony Lindgren wrote:
(...)
#define GPMC_ECC1_RESULT0x200
+#define GPMC_ECC_BCH_RESULT_0 0x240
Can you please add a comment here saying something like:
#define GPMC_ECC_BCH_RESULT_0 0x240 /* Not
* Ivan Djelic ivan.dje...@parrot.com [120425 11:33]:
Hi Tony,
Thanks for the review,
On Wed, Apr 25, 2012 at 06:03:14PM +0100, Tony Lindgren wrote:
(...)
#define GPMC_ECC1_RESULT0x200
+#define GPMC_ECC_BCH_RESULT_0 0x240
Can you please add a comment here saying
On Wed, 25 Apr 2012 14:54:54 +0200 (CEST) Thomas Gleixner
t...@linutronix.de wrote:
On Wed, 25 Apr 2012, NeilBrown wrote:
On Wed, 25 Apr 2012 10:50:15 +0200 (CEST) Thomas Gleixner
t...@linutronix.de wrote:
On Wed, 25 Apr 2012, NeilBrown wrote:
Level triggered interrupts do not
On 04/24/2012 04:05 PM, Daniel Lezcano wrote:
This patchset makes some cleanup on these cpuidle drivers
and consolidate the code across both architecture.
Tested on OMAP3 (igepV2).
Partially tested on OMAP4 (pandaboard), without offlining the cpu1.
Hi,
could be this patchset considered for
+alsa-devel list
On 04/25/2012 01:19 AM, Tomi Valkeinen wrote:
On Tue, 2012-04-24 at 23:48 -0500, Ricardo Neri wrote:
On 04/23/2012 08:01 AM, Tomi Valkeinen wrote:
On Wed, 2012-03-28 at 16:38 -0600, Ricardo Neri wrote:
Implement the DSS device driver audio support interface in the HDMI
panel
Hi Tony,
I was wondering if you've had the time to take a look at these patches.
Thanks!
Ricardo
On 04/17/2012 07:40 PM, Ricardo Neri wrote:
This set of patches is intended to add the platform devices for the ASoC
HDMI drivers when not using device tree. For this, I took an approach similar
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 05:52:26, Paul Walmsley wrote:
A few questions while reviewing this patch:
On Tue, 3 Apr 2012, Vaibhav Hiremath wrote:
AM33XX PRCM module consist of, various clockdomains, in all
total we have 18 clockdomains
On Tue, 24 Apr 2012, Kevin Hilman wrote:
Iteration over all power domains in the idle path is unnecessary since
only power domains that are transitioning need to be accounted for.
Also PRCM register accesses are known to be expensive, so the
additional latency added to the idle path is
On Tue, Apr 24, 2012 at 2:45 AM, Vaibhav Hiremath hvaib...@ti.com wrote:
Current OMAP code supports couple of clocksource options based
on compilation flag (CONFIG_OMAP_32K_TIMER). The 32KHz sync-timer
and a gptimer which can run on 32KHz or system clock (e.g 38.4 MHz).
So there can be 3
On Wed, Apr 25, 2012 at 7:15 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Wed, Apr 25, 2012 at 06:24:14PM +0530, DebBarma, Tarun Kanti wrote:
On Wed, Apr 25, 2012 at 12:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Wed, Apr 25, 2012 at 10:04 AM, DebBarma, Tarun
Hi Tony,
On Wed, Apr 25, 2012 at 22:14:25, Tony Lindgren wrote:
Once driver is acceptable, platform code for other peripherals
connected via GPMC would be adapted to make use of GPMC driver. And
then the board modifications. But before that HWMOD entry has to be
populated for respective
On Wed, 2012-04-25 at 19:01 +0200, Janusz Krzysztofik wrote:
Both drivers use separate subsets of registers that belong to the OMAP1
MPU I/O device, but are used for controlling different sets of I/O pins.
The NAND driver reads/writes the folowing registers:
- OMAP_MPUIO_INPUT_LATCH,
-
Hi Tony,
On Wed, Apr 25, 2012 at 22:17:26, Tony Lindgren wrote:
Obviously we can't merge any of this if until all the board-*.c files
are changed and tested.
Can you maybe still keep the old interfaces in addition to the new ones
so we can do the conversion one board-*.c file at a time
On Thu, Apr 26, 2012 at 10:06:40, Russ Dill wrote:
On Tue, Apr 24, 2012 at 2:45 AM, Vaibhav Hiremath hvaib...@ti.com wrote:
Current OMAP code supports couple of clocksource options based
on compilation flag (CONFIG_OMAP_32K_TIMER). The 32KHz sync-timer
and a gptimer which can run on 32KHz
Hi,
+/*
+ * clkdiv32 is generated from fixed division of 732.4219
+ */
+static struct clk clkdiv32k_ick = {
+ .name = clkdiv32k_ick,
+ .clkdm_name = clk_24mhz_clkdm,
+ .rate = 32768,
+ .parent = clk_24mhz,
+ .enable_reg =
On Thu, Apr 26, 2012 at 08:49:28, Paul Walmsley wrote:
On Wed, 25 Apr 2012, Hiremath, Vaibhav wrote:
On Wed, Apr 25, 2012 at 05:52:26, Paul Walmsley wrote:
A few questions while reviewing this patch:
On Tue, 3 Apr 2012, Vaibhav Hiremath wrote:
AM33XX PRCM module consist of,
From: G, Manjunath Kondaiah manj...@ti.com
Keypad controller register offsets are different for omap4
and omap5. Handle these offsets through static mapping and
assign these mappings during run time.
Tested on omap4430 sdp with 3.4-rc3.
Tested on omap5430evm with 3.1-custom kernel.
Cc: Andrew
On Wed, Apr 25, 2012 at 10:42 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Thu, Apr 26, 2012 at 10:06:40, Russ Dill wrote:
On Tue, Apr 24, 2012 at 2:45 AM, Vaibhav Hiremath hvaib...@ti.com wrote:
Current OMAP code supports couple of clocksource options based
on compilation flag
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