On Thursday 13 September 2012 03:57 AM, Kevin Hilman wrote:
Shubhrajyoti D shubhrajy...@ti.com writes:
[...]
This is the cleanup only series.
Tested on omap4sdp and 3430sdp.
It would be extremely helpful if you would describe how this was tested.
And for me, it would be a source of
On Wed, Sep 12, 2012 at 22:51:55, Cousson, Benoit wrote:
+ Paul
Hi Anil,
On 08/31/2012 11:37 AM, AnilKumar Ch wrote:
Add DT OPP table for AM33XX family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
Also adds cpu0 supply name to the corresponding
Hi,
On Thu, Sep 13, 2012 at 11:34:48AM +0530, Shubhrajyoti wrote:
On Thursday 13 September 2012 03:57 AM, Kevin Hilman wrote:
Shubhrajyoti D shubhrajy...@ti.com writes:
[...]
This is the cleanup only series.
Tested on omap4sdp and 3430sdp.
It would be extremely helpful if you
From: Vaibhav Bedia vaibhav.be...@ti.com
In some cases mmc_suspend_host() is not able to claim the
host and proceed with the suspend process. The core returns
-EBUSY to the host controller driver. Unfortunately, the
host controller driver does not pass on this information
to the PM core and hence
On Wed, Sep 12, 2012 at 10:27 PM, Tony Lindgren t...@atomide.com wrote:
* Peter Ujfalusi peter.ujfal...@ti.com [120911 01:54]:
With pinctrl-single,bits it is possible to update just part of the register
within the pinctrl-single,function-mask area.
This is useful when one register configures
On Thursday 13 September 2012 11:34 AM, Shubhrajyoti wrote:
At least on 3530/Overo and 3730/Overo, CORE no longer hits retenion (or
off) during idle.
I dont have an Overo, anyways will see if I can get one
However on beagleXm even off count increases
/ # grep ^core_pwrdm
On Thu, Sep 13, 2012 at 2:34 AM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Jean Pihet jean.pi...@newoldbits.com writes:
Here is a re-spin after some comments and suggestions after review
and discussions.
Implement the functional states for the power domains:
- unify the API to use the
From a00cbfadc0053a3c21812593997a1b7338234a9f Mon Sep 17 00:00:00 2001
From: Ramesh Gupta G grgu...@ti.com
Date: Thu, 13 Sep 2012 11:43:20 +0530
Subject: [PATCH v6 0/2] ARM: New cache API for iommu
This patch series is the next version to
- add a new cache maintenance api to support non-coherent
On Tue, Sep 11, 2012 at 11:13:26, S, Venkatraman wrote:
On Tue, Sep 4, 2012 at 6:38 PM, Hebbar, Gururaja gururaja.heb...@ti.com
wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
In some cases mmc_suspend_host() is not able to claim the
host and proceed with the suspend process. The core
From e88037801393f86ade3c79bcc900d3c84d989655 Mon Sep 17 00:00:00 2001
From: Ramesh Gupta G grgu...@ti.com
Date: Wed, 12 Sep 2012 13:07:26 +0530
Subject: [PATCH v6 1/2] ARM: new cache maintenance api for iommu
Non-coherent IOMMU drivers need to make sure
that the data held in the caches is
From a00cbfadc0053a3c21812593997a1b7338234a9f Mon Sep 17 00:00:00 2001
From: Ramesh Gupta G grgu...@ti.com
Date: Wed, 12 Sep 2012 19:05:29 +0530
Subject: [PATCH v6 2/2] OMAP:IOMMU:flush L1 and L2 caches
OMAP IOMMU need to make sure that data in the L1 and L2 caches
is visible to the MMU hardware
Marc,
On Wed, Sep 12, 2012 at 18:32:53, Marc Kleine-Budde wrote:
On 09/12/2012 02:48 PM, AnilKumar, Chimata wrote:
Hi Marc,
On Tue, Sep 04, 2012 at 12:57:18, Marc Kleine-Budde wrote:
On 09/04/2012 08:14 AM, AnilKumar, Chimata wrote:
Marc,
Thanks for the comments,
On Tue, Sep
HI Kevin,
On Thu, Sep 13, 2012 at 1:47 AM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Jean Pihet jean.pi...@newoldbits.com writes:
Trace the power domain transitions using the functional power states,
which include the power and logic states.
Just to be clear, this means that a trace
On Thu, Sep 13, 2012 at 2:11 AM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Jean Pihet jean.pi...@newoldbits.com writes:
The newly added code for functional power states re-defines the
API to query and control the power domains settings.
The API is now split in the following parts in
Move pm_runtime_enable/disable calls to c_can.c driver. Current
implementation is such that platform driver is doing pm_runtime
enable/disable and core driver is doing put_sync/get_sync.
PM runtime calls should be invoked if there is a valid device
pointer from platform driver so moving
On Thu, Sep 13, 2012 at 1:47 AM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Use of smp_processor_id() here will require the same care as pointed out
by Roger Quadros in [PATCH] perf: Use raw_smp_processor_id insted of
smp_processor_id.
BTW it looks like get_cpu and put_cpu is the way to
On 09/13/2012 09:52 AM, Linus Walleij wrote:
On Wed, Sep 12, 2012 at 10:27 PM, Tony Lindgren t...@atomide.com wrote:
* Peter Ujfalusi peter.ujfal...@ti.com [120911 01:54]:
With pinctrl-single,bits it is possible to update just part of the register
within the pinctrl-single,function-mask area.
On Wed, 2012-09-12 at 16:11 -0700, Kevin Hilman wrote:
Paul Walmsley p...@pwsan.com writes:
[...]
It kind of looks to me like there are two or three separate sets within
the series. My feeling is that Kevin should take the first two, then I
should take the rest other than 6 and 7.
On 09/13/2012 09:28 AM, AnilKumar Ch wrote:
Move pm_runtime_enable/disable calls to c_can.c driver. Current
implementation is such that platform driver is doing pm_runtime
enable/disable and core driver is doing put_sync/get_sync.
PM runtime calls should be invoked if there is a valid device
On Wed, Sep 12, 2012 at 02:46:56PM +0300, Peter Ujfalusi wrote:
Hello,
This series will switch the OMAP audio to use dmaengine.
The final patch which does the switch was based on Russell King's earlier
patch.
I'm fine with this from the ASoC side but it sounds like you're going to
respin
Marc,
On Thu, Sep 13, 2012 at 13:18:07, Marc Kleine-Budde wrote:
On 09/13/2012 09:28 AM, AnilKumar Ch wrote:
Move pm_runtime_enable/disable calls to c_can.c driver. Current
implementation is such that platform driver is doing pm_runtime
enable/disable and core driver is doing
On 09/13/2012 09:24 AM, AnilKumar, Chimata wrote:
Marc,
On Wed, Sep 12, 2012 at 18:32:53, Marc Kleine-Budde wrote:
On 09/12/2012 02:48 PM, AnilKumar, Chimata wrote:
Hi Marc,
On Tue, Sep 04, 2012 at 12:57:18, Marc Kleine-Budde wrote:
On 09/04/2012 08:14 AM, AnilKumar, Chimata wrote:
Marc,
Hi Kevin,
Since this series is already merged, I suggest that the problem patch be
reverted, at least for v3.7 and until the problem is better understood
and tested.
I thought I'll give you guys some more days to fix the problem before
reverting.
With that patch reverted, all my PM tests
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson b-cous...@ti.com wrote:
[...]
Silly question: Don't we have one arch-timer per
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson b-cous...@ti.com
On 09/13/2012 11:11 AM, Mark Brown wrote:
On Wed, Sep 12, 2012 at 02:46:56PM +0300, Peter Ujfalusi wrote:
Hello,
This series will switch the OMAP audio to use dmaengine.
The final patch which does the switch was based on Russell King's earlier
patch.
I'm fine with this from the ASoC side
On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Sep
On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson b-cous...@ti.com wrote:
On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at
On Thu, Sep 13, 2012 at 3:30 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson b-cous...@ti.com wrote:
On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On
From: Santosh Shilimkar santosh.shilim...@ti.com
The ARMv7 processor setup function __v7_setup() cleans and invalidates the
CPU cache before enabling MMU to start the CPU with a clean CPU local cache.
But on ARMv7 architectures like Cortex-[A15/A8], this code will end
up flushing the L2
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes
the L2 unified cache.
When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.
Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of
ARM v7 architecture introduces the concept of cache levels and registers to
probe and manage cache levels accordingly.
This patch adds v7 support for cache LoUIS (Level of Unification Inner
Shareable) operations and defines a function that allows to clean and
invalidate data caches up to LoUIS.
ARM v7 architecture introduced the concept of cache levels and related
coherency requirements. New processors like A7 and A15 embed an
L2 unified cache controller that becomes part of the cache level
hierarchy. Some operations in the kernel like cpu_suspend and __cpu_disable
does not require a
This patch series provides an update of a previous posting:
http://www.spinics.net/lists/arm-kernel/msg169075.html
Main changes:
- Changed the new API to Level of Unification Inner Shareable (LoUIS)
- Fixed a pointer bug in __cpu_suspend_save code update
- Added patches to update
From: Santosh Shilimkar santosh.shilim...@ti.com
On ARMv7 based SOC with an integrated L2 cache, there is a need
to have a flush API to operate on each cache level. In few low
power modes, L2 cache is retained whereas L1 is lost. The current
v7_flush_dcache_all(), flushes all the levels and it
On Thu, Sep 06, 2012 at 19:36:08, Hunter, Jon wrote:
On 09/06/2012 12:07 AM, Vaibhav Hiremath wrote:
On 9/6/2012 12:34 AM, Jon Hunter wrote:
Errata Titles:
i103: Delay needed to read some GP timer, WD timer and sync timer registers
after wakeup (OMAP3/4)
i767: Delay needed
On Thu, Sep 06, 2012 at 21:31:21, Hunter, Jon wrote:
On 09/06/2012 09:20 AM, Jon Hunter wrote:
On 09/06/2012 07:57 AM, Vaibhav Hiremath wrote:
On 9/6/2012 12:34 AM, Jon Hunter wrote:
Currently the dmtimer posted mode is being enabled when the function
__omap_dm_timer_reset() is
On Thu, Sep 06, 2012 at 20:50:27, Hunter, Jon wrote:
On 09/06/2012 09:42 AM, Jon Hunter wrote:
On 09/06/2012 09:06 AM, Jon Hunter wrote:
On 09/06/2012 12:07 AM, Vaibhav Hiremath wrote:
On 9/6/2012 12:34 AM, Jon Hunter wrote:
Errata Titles:
i103: Delay needed to read some GP
On Mon, Sep 03, 2012 at 11:23:22PM +0300, Aaro Koskinen wrote:
Add i2c driver to enable access to devices behind CBUS on Nokia Internet
Tablets.
The patch also adds CBUS I2C configuration for N8x0 which is one of the
users of this driver.
Cc: linux-...@vger.kernel.org
Acked-by: Felipe
On Thu, Sep 13, 2012 at 11:20:46AM +0100, Lorenzo Pieralisi wrote:
ARM v7 architecture introduced the concept of cache levels and related
coherency requirements. New processors like A7 and A15 embed an
L2 unified cache controller that becomes part of the cache level
hierarchy. Some operations
On Mon, Aug 13, 2012 at 8:23 PM, Munegowda, Keshava
keshava_mgo...@ti.com wrote:
On Mon, Aug 13, 2012 at 7:39 PM, Felipe Balbi ba...@ti.com wrote:
On Mon, Aug 13, 2012 at 06:52:13PM +0530, Munegowda, Keshava wrote:
On Fri, Jul 27, 2012 at 5:44 PM, Munegowda, Keshava
keshava_mgo...@ti.com
DSS HW on OMAP4 onwards supports a new pipeline called writeback. Unlike other
pipelines(called overlays in OMAPDSS), writeback takes pixel data from an
overlay output or a overlay manager output and writes it back into a specified
address in memory.
writeback pipeline allows us to take benefit
The DISPC pipeline register names in the TRM for setting the buffer size and
the output size are a bit misleading, for example, there are different register
names for setting the buffer size for VID and GFX pipes. Things get more
confusing when considering writeback pipeline.
Rename the functions
Writeback pipeline has similar registers compared to graphics and video pipes
for setting base addresses, color conversion, row inc, pix inc etc. Rename these
functions from dispc_ovl_* to dispc_plane_*. The actual registers are kept as
DISPC_OVL_* only to prevent too much change.
All functions
Currently, the functions below take the omap_plane parameter and derive the
overlay caps within them. Pass the overlay caps as a parameter to the function
to allow these to be used by writeback too.
- dispc_plane_set_zorder()
- dispc_plane_set_pre_mult_alpha()
- dispc_plane_setup_global_alpha()
-
Add position and replication as overlay caps, and pass overlay caps as an
argument to the corresponding functions. Adding position and replication to
overlay caps seems a bit unnecessary, but it allows us to use the
corresponding functions for writeback too.
These caps will be set for all
Add a new static function called dispc_plane_setup(). This function is used by
dispc_ovl_setup() to configure the overlay registers.
This split is done so that dispc_wb_setup() can reuse the common overlay related
registers configured in dispc_plane_setup().
Signed-off-by: Archit Taneja
Scaling calculations for an overlay are done by comparing pixel clock of the
connected overlay manager and the core clock of DISPC. The pixel clock is the
output rate of the scalar. The scalar block needs to provide pixels at this rate
since the manager is connected to a panel, which has real time
The struct omap_overlay_info passed to dispc_ovl_setup() is used to configure
DISPC registers. It shouldn't modify the overlay_info structure. The pos_y field
was being changed in dispc_ovl_setup in the case of interlaced displays. Fix
this and const qualifier to the omap_overlay_info argument.
Writeback pipeline has an identical scalar block as in video pipelines. Rename
the scalar related function from dispc_ovl_* to dispc_plane_*. The actual
registers are kept as DISPC_OVL_* only to prevent too much change.
All functions which are common to overlays and writeback are to be named as
In the function dispc_plane_set_scaling_uv(), create a parameter which tells if
we want to upscale or downscale the chroma plane.
Downscaling of chroma is required by writeback pipeline for converting the input
YUV444 color format to YUV422 or NV12.
Signed-off-by: Archit Taneja arc...@ti.com
---
Since writeback has many overlay like properties, and most of it's registers are
similar to that of overlays, it's possible to reuse most of the overlay related
DISPC code for writeback when considering it as a plane. Writeback was added as
a plane in the omap_plane field as OMAP_DSS_WB.
Add the
Writeback uses the WB_PICTURE_SIZE register to define the size of the content
written to memory, this is the output of the scalar. It uses the WB_SIZE
register to define the size of the content coming from the overlay/manager to
which it is connected, this is the input to the scalar. This naming
The scalar output rate for writeback pipeline when configured in memory to
memory mode isn't a fixed rate, it can increase or reduce based on the time
it needs to downscale. It also depends on the rate at which it can receive
and push out data from/to the interconnect.
Set the scalar output rates
When converting YUYV444 content to YUV422 or NV12 formats through writeback
pipeline, the scalar needs to downscale the chroma plane. Ensure that chroma
is downscaled when the pipeline is writeback.
Signed-off-by: Archit Taneja arc...@ti.com
---
drivers/video/omap2/dss/dispc.c |2 +-
1 file
The bit YUVCHROMARESAMPLING isn't there for writeback in DISPC_WB_ATTRIBUTES2.
It isn't there because we don't upsample chroma like for video pipelines, we
downsample chroma in writeback to get YUV422 or NV12 formats from the YUV444
input.
Ignore this bit in dispc_ovl_set_scaling_uv() if the
Writeback can take input from either one of the overlays, or one of the overlay
managers. Add an enum which represents the channel_in for writeback, and maps
to the register field programming.
Add a function to configure channel in for writeback. This will be used later in
APPLY.
Signed-off-by:
Writeback pipeline uses fifo and burst related IP similar to what the graphics
and video pipe have. Rename the related functions from dispc_ovl_* to
dispc_plane_*. The actual registers are kept as DISPC_OVL_* only to prevent too
much change.
All functions which are common to overlays and
Create struct omap_dss_writeback_info, this is similar to omap_overlay_info,
the major difference is that there is no parameter which describes the input
size to writeback, this is because this is always fixed, and decided by the
connected overlay or overlay manager. One more difference is that
Configure some of the writeback specific parameters in dispc_wb_setup(). The
writeback parameters configured are:
truncation: This needs to be set if the color depth input to writeback is more
than the color depth of the color mode we want to store in memory.
writeback mode: This configures
Extend the DISPC fifo functions to also configure the writeback FIFO thresholds.
The most optimal configuration for writeback is to push out data to the
interconnect the moment writeback pushes enough pixels in the FIFO to form a
burst. This reduces the chance of writeback overflowing it's FIFO.
Add functions to enable writeback, and set/check state of GO bit. These bits are
identical in behaviour with the corresponding overlay manager bits. Configure
them in a similar way to mgr_enable() and mgr_go_* functions. Add a helper to
get the FRAMEDONE irq corresponding to writeback.
Writeback pipeline receives RGB data from one of the overlays or one of the
overlay managers. If the target color mode is YUV422 or NV12, we need to convert
the RGB pixels to YUV. The scalar in WB then converts it to the target color
mode.
Hence, the color conversion coefficients that need to be
On Thu, Sep 13, 2012 at 11:20:46AM +0100, Lorenzo Pieralisi wrote:
+/*
+ * Flush caches up to Level of Unification Inner Shareable
+ */
+#ifdef MULTI_CACHE
+#define flush_cache_louis() cpu_cache.flush_kern_cache_louis()
+#else
+#define flush_cache_louis() __cpuc_flush_kern_all()
On Thu, Sep 13, 2012 at 11:20:49AM +0100, Lorenzo Pieralisi wrote:
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache
On Thu, Sep 13, 2012 at 01:36:04PM +0100, Russell King - ARM Linux wrote:
On Thu, Sep 13, 2012 at 11:20:46AM +0100, Lorenzo Pieralisi wrote:
+/*
+ * Flush caches up to Level of Unification Inner Shareable
+ */
+#ifdef MULTI_CACHE
+#define flush_cache_louis()
On Thu, Sep 13, 2012 at 6:23 PM, Dave Martin dave.mar...@linaro.org wrote:
On Thu, Sep 13, 2012 at 11:20:49AM +0100, Lorenzo Pieralisi wrote:
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore.
On Thu, Sep 13, 2012 at 12:39:49PM +0100, Dave Martin wrote:
We could introduce something like CONFIG_ARM_HAVE_CACHEFLUSH_LOUIS, and
do:
asm/glue-cache.h
#ifndef MULTI_CACHE
#ifdef CONFIG_HAVE_ARM_CACHEFLUSH_LOUIS
#define __cpuc_flush_kern_cache_louis __glue(_CACHE,_flush_kern_cache_louis)
On Thu, Sep 13, 2012 at 06:31:35PM +0530, Shilimkar, Santosh wrote:
In the series, there is patch [PATCH 3/6] which adds an
API which let you operate on a specific level.
Which is introduced but as far as I can see, is never used in the patch
set. Therefore, it shouldn't be introduced.
We've
On Thu, Sep 13, 2012 at 6:38 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Sep 13, 2012 at 06:31:35PM +0530, Shilimkar, Santosh wrote:
In the series, there is patch [PATCH 3/6] which adds an
API which let you operate on a specific level.
Which is introduced but as far as
The audio stack used omap_stop_dma/omap_start_dma to pause/resume the DMA.
This method has been used for years on OMAP based products.
We only allow pause/resume when the DMA has been configured in cyclic mode
which is used by the audio stack.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Change the parameter list of device_prep_dma_cyclic() so the DMA drivers
can receive the no_wakeup request coming from client drivers.
This feature can be used during audio operation to disable all audio
related interrupts.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Nicolas Ferre
Based on the format of the stream the omap-pcm can decide alone what data
type should be used with by the sDMA.
Keep the possibility for OMAP dai drivers to tell omap-pcm if they want to
use different data type. This is needed for the omap-hdmi for example which
needs 32bit data type even if the
Original author: Russell King rmk+ker...@arm.linux.org.uk
Switch the omap-pcm to use dmaengine.
Certain features are not supported by after dmaengine conversion:
1. No period wakeup mode
DMA engine has no way to communicate this information through
standard channels.
Signed-off-by: Peter
To help the driver to get the correct memory range to access McPDM
registers.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
Set the dma_data for the stream (snd_soc_dai_set_dma_data) at dai_startup
time so omap-pcm will have access to the needed information regarding to
the DMA channel earlier.
This is needed for the clean dmaengine support.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
Instead of the OMAP DMA data type definition the data_type will be used to
specify the number of bits the DMA word should be configured or 0 in case
when based on the stream's format the omap-pcm can decide the needed DMA
word size.
This feature is needed for the omap-hdmi where the sDMA need to
omap-pcm can figure out the correct dma_type based on the stream's format.
In this way we can get rid of the plat/dma.h include from these drivers.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
sound/soc/omap/omap-dmic.c | 2 --
sound/soc/omap/omap-mcbsp.c | 3 ---
When src_maxburst/dst_maxburst is set to 0 by the users of cyclic DMA
(mostly audio) indicates that we should configure the omap DMA to element
sync mode instead of packet mode.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Russell King rmk+ker...@arm.linux.org.uk
---
Hello,
Changelog:
- Support for pause/resume for OMAP audio via dmaengine
- dmaengine: support for NO_PERIOD_WAKEUP in cyclic mode
- OMAP to keep supporting NO_PERIOD_WAKEUP for audio
- Other plaforms can also try to enable this mode since we have now generic
interface to do so.
This series
When McBSP is configured in threshold mode we can use sDMA packet mode in
all cases.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
sound/soc/omap/omap-mcbsp.c | 47 -
1 file changed, 17 insertions(+), 30 deletions(-)
diff --git
The omap-pcm platform driver no longer needs this parameter to select
between ELEMENT and PACKET mode. The selection is based on the configured
packet_size.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
sound/soc/omap/omap-dmic.c | 1 -
sound/soc/omap/omap-hdmi.c | 1 -
Get the needed resources in a correct way and avoid using defines for them.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
sound/soc/omap/omap-mcpdm.c | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/sound/soc/omap/omap-mcpdm.c
Since we only have element or packet synchronization we can use the
dma_data-packet_size to select the desired mode:
if packet_size is 0 we use ELEMENT mode
if packet_size is not 0 we use PACKET mode for sDMA synchronization.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
When requested disable all DMA interrupts for the channel. In this mode
user space does not expect periodic reports from kernel about the progress
of the audio stream - PulseAudio for example support this type of mode.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Russell King
The dmaengine_prep_dma_cyclic() function primarily used by audio for cyclic
transfer required by ALSA.
With this new parameter it is going to be possible to enable the
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP mode on platforms where it is possible.
This patch only changes the public API first. Followup
On Thu, Sep 13, 2012 at 02:03:34PM +0100, Russell King - ARM Linux wrote:
On Thu, Sep 13, 2012 at 12:39:49PM +0100, Dave Martin wrote:
We could introduce something like CONFIG_ARM_HAVE_CACHEFLUSH_LOUIS, and
do:
asm/glue-cache.h
#ifndef MULTI_CACHE
#ifdef
AnilKumar Ch anilku...@ti.com writes:
Move pm_runtime_enable/disable calls to c_can.c driver. Current
implementation is such that platform driver is doing pm_runtime
enable/disable and core driver is doing put_sync/get_sync.
PM runtime calls should be invoked if there is a valid device
On Thu, Sep 13, 2012 at 01:53:48PM +0100, Dave Martin wrote:
On Thu, Sep 13, 2012 at 11:20:49AM +0100, Lorenzo Pieralisi wrote:
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For
On 09/13/2012 04:14 PM, Kevin Hilman wrote:
AnilKumar Ch anilku...@ti.com writes:
Move pm_runtime_enable/disable calls to c_can.c driver. Current
implementation is such that platform driver is doing pm_runtime
enable/disable and core driver is doing put_sync/get_sync.
PM runtime calls
On Thu, Sep 13, 2012 at 02:01:35PM +0100, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 6:23 PM, Dave Martin dave.mar...@linaro.org wrote:
[...]
LoUIS matches the power domain affected by turning a single CPU off
on most (all?) current v7 SoCs where this matters, but only by
Felipe Balbi ba...@ti.com writes:
[...]
I just ran same tests on pandaboard and i2c is suspended actually,
though no power domain transitions to RET. Do we not have retention
while idle on pandaboard ?
Not for CORE. Only CPUx and MPU domains will be transitioning on OMAP4,
and then, only
On Thu, Sep 13, 2012 at 12:53:09PM +0200, Wolfram Sang wrote:
On Mon, Sep 03, 2012 at 11:23:22PM +0300, Aaro Koskinen wrote:
Add i2c driver to enable access to devices behind CBUS on Nokia Internet
Tablets.
The patch also adds CBUS I2C configuration for N8x0 which is one of the
users
When the omap2 nand flash driver is used, the nand-disk led trigger does not
work due to nand_wait_ready not being called.
This patch exports the trigger from nand_base.c, letting specific drivers
such omap2 control the led as appropriate.
Signed-off-by: Raphael Assenat r...@8d.com
diff --git
On 09/13/2012 03:37 PM, Peter Ujfalusi wrote:
The dmaengine_prep_dma_cyclic() function primarily used by audio for cyclic
transfer required by ALSA.
With this new parameter it is going to be possible to enable the
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP mode on platforms where it is possible.
This
On Thu, Sep 13, 2012 at 05:27:09PM +0200, Lars-Peter Clausen wrote:
Hm... Do you think it would work as well if we implement this by setting the
callback for the descriptor to NULL? If the callback is NULL there is
nothing to at the end of a transfer/period and the dma engine driver may
choose
Add device tree matching table support to lis3lv02d_i2c driver. If
the driver data is passed from device tree, then this driver picks
up platform data from device node through common/generic lis3lv02d.c
driver.
Signed-off-by: AnilKumar Ch anilku...@ti.com
---
First patch adds device tree support to lis3lv02d_i2c driver and
second patch adds platform data for lis331dlh driver to am335x
EVM. These patches were tested on AM335x-EVM.
AnilKumar Ch (2):
lis3: lis3lv02d_i2c: Add device tree support
ARM: dts: AM33XX: Add lis331dlh device tree data to
Add lis331dlh device tree data to am335x-evm.dts. In AM335x EVM
lis331dlh accelerometer is connected to I2C2 bus. So this patch
change the status to okay to use I2C2 bus. Also added all the
required platform data to am335x-evm.
Signed-off-by: AnilKumar Ch anilku...@ti.com
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