On Oct 22, 2008, at 3:59 AM, Régis Odeyé wrote:
Hello Everyone,
I'm looking for some information about the Extended Addressing Mode
(XAEN bit of HID0 register) of PPC32 support in Linux.
I do not see anything in the main kernel tree but there may be some
patches available ?
Any
Kumar Gala wrote:
On Oct 22, 2008, at 3:59 AM, Régis Odeyé wrote:
Hello Everyone,
I'm looking for some information about the Extended Addressing Mode
(XAEN bit of HID0 register) of PPC32 support in Linux.
I do not see anything in the main kernel tree but there may be some
patches available
On Oct 22, 2008, at 7:59 AM, Régis Odeyé wrote:
Kumar Gala wrote:
On Oct 22, 2008, at 3:59 AM, Régis Odeyé wrote:
Hello Everyone,
I'm looking for some information about the Extended Addressing
Mode (XAEN bit of HID0 register) of PPC32 support in Linux.
I do not see anything in the main
Kumar Gala wrote:
So we have XAEN support in the tree.. however non-contiguous is
something you'll have to work on yourself. Patches are welcome for this
OK. I will let you know about this.
Where can I glance through Becky patches ?
This is the bulk:
Kumar Gala wrote:
On Oct 22, 2008, at 7:59 AM, Régis Odeyé wrote:
of ram. So I need 4GB+IOs (~1GB) of physical addressing space.
My plan is to put a part of this ram above of 4GB to keep accesses to
the IOs below the 4GB limit. It means non-contiguous ram addressing
and XAEN features to
On Oct 22, 2008, at 8:42 AM, Matt Sealey wrote:
Kumar Gala wrote:
On Oct 22, 2008, at 7:59 AM, Régis Odeyé wrote:
of ram. So I need 4GB+IOs (~1GB) of physical addressing space.
My plan is to put a part of this ram above of 4GB to keep accesses
to the IOs below the 4GB limit. It means
Matt Sealey wrote:
I'd also be interested in any work done to enable non-contiguous
memory areas. Reading the docs for the MPC8641D though I am not sure
you can set up LAWs for it?
One thing I wanted to try was installing 4GB in a system and
overlapping IO (since there is very little of it
Kumar Gala wrote:
On Oct 22, 2008, at 8:42 AM, Matt Sealey wrote:
So to confirm, XAEN support through Becky's patches does support the
MPC8641D/e600 cores?
Yes, its the only part that has XAEN.
Okay I saw a lot of e500/BookE support go past but nothing
specific :)
NOT supported
Kumar Gala wrote:
Your bigger issue is if you can setup the DDR controller for the hole
you want.
I just remembered;;
~~
The CCSR window always takes precedence over all local access
windows. However, the CCSR window must not overlap an LAW that
maps to the DDR controller. Otherwise,
On Oct 22, 2008, at 9:19 AM, Matt Sealey wrote:
Kumar Gala wrote:
On Oct 22, 2008, at 8:42 AM, Matt Sealey wrote:
So to confirm, XAEN support through Becky's patches does support
the MPC8641D/e600 cores?
Yes, its the only part that has XAEN.
Okay I saw a lot of e500/BookE support go
On Oct 22, 2008, at 9:22 AM, Matt Sealey wrote:
Kumar Gala wrote:
Your bigger issue is if you can setup the DDR controller for the
hole you want.
I just remembered;;
~~
The CCSR window always takes precedence over all local access
windows. However, the CCSR window must not overlap an
Kumar Gala wrote:
On Oct 22, 2008, at 9:19 AM, Matt Sealey wrote:
Kumar Gala wrote:
On Oct 22, 2008, at 8:42 AM, Matt Sealey wrote:
So to confirm, XAEN support through Becky's patches does support the
MPC8641D/e600 cores?
Yes, its the only part that has XAEN.
Okay I saw a lot of
Kumar Gala wrote:
On Oct 22, 2008, at 9:22 AM, Matt Sealey wrote:
~~
The CCSR window always takes precedence over all local access windows.
However, the CCSR window must not overlap an LAW that maps to the DDR
controller. Otherwise, undefined behavior occurs.
~~
So, it's not really
On Oct 22, 2008, at 1:11 PM, Matt Sealey wrote:
Kumar Gala wrote:
On Oct 22, 2008, at 9:19 AM, Matt Sealey wrote:
Kumar Gala wrote:
On Oct 22, 2008, at 8:42 AM, Matt Sealey wrote:
So to confirm, XAEN support through Becky's patches does support
the MPC8641D/e600 cores?
Yes, its the
On Wed, 2008-10-22 at 08:08 -0500, Kumar Gala wrote:
We are developing a board based on Freescale 8641D which can get
4GB
of ram. So I need 4GB+IOs (~1GB) of physical addressing space.
My plan is to put a part of this ram above of 4GB to keep accesses
to the IOs below the 4GB limit.
Becky Bruce wrote:
On Oct 22, 2008, at 1:11 PM, Matt Sealey wrote:
Yeah so I saw BookE and e500 stuff go past but nothing specific for
e600/XAEN. I mailed Becky and got no response. I'm glad to know it's
in there though, somewhere.
Huh? I have one mail from you, on Sep 1, to which I
Benjamin Herrenschmidt wrote:
On Wed, 2008-10-22 at 08:08 -0500, Kumar Gala wrote:
We are developing a board based on Freescale 8641D which can get
4GB
of ram. So I need 4GB+IOs (~1GB) of physical addressing space.
My plan is to put a part of this ram above of 4GB to keep accesses
to the
On Wed, 2008-10-22 at 17:21 -0500, Matt Sealey wrote:
Because we're Genesi! And we have a firmware solution that
kind of has to keep 32-bit pointers in the unlikely event that
someone actually uses the client interface (besides yaboot!).
Having I/O in the 36-bit range could cause all
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