When VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT is set we skip NIR
linking optimisations and only run over the NIR optimisation loop
once similar to the GLSLOptimizeConservatively constant used by
some GL drivers.
We need to run over the opts at least once to avoid errors in LLVM
(e.g. dead vars
CC:
Signed-off-by: Jan Vesely
---
src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
On Mon, May 07, 2018 at 11:04:20AM -0700, Nanley Chery wrote:
> On Mon, May 07, 2018 at 03:06:29PM +0300, Pohjolainen, Topi wrote:
> > On Thu, May 03, 2018 at 12:03:53PM -0700, Nanley Chery wrote:
> > > We have enough information to determine the optimal flags internally.
> > > ---
> > >
For the series:
Reviewed-by: Marek Olšák
Marek
On Mon, May 7, 2018 at 11:05 PM, Jan Vesely wrote:
> CC:
> Signed-off-by: Jan Vesely
> ---
> src/gallium/drivers/r600/evergreen_compute.c
On Mon, May 07, 2018 at 10:11:39AM -0700, Nanley Chery wrote:
> On Mon, May 07, 2018 at 11:30:15AM +0300, Pohjolainen, Topi wrote:
> > On Thu, May 03, 2018 at 12:03:51PM -0700, Nanley Chery wrote:
> > > The indirect clear color isn't correctly tracked in
> > > intel_miptree::fast_clear_color. The
On Mon, May 07, 2018 at 11:30:12AM -0700, Nanley Chery wrote:
> On Mon, May 07, 2018 at 04:12:24PM +0300, Pohjolainen, Topi wrote:
> > On Thu, May 03, 2018 at 12:03:56PM -0700, Nanley Chery wrote:
> > > There isn't much that changes between the aux allocation functions.
> > > Remove the duplicated
On Mon, May 07, 2018 at 11:38:38AM -0700, Nanley Chery wrote:
> On Mon, May 07, 2018 at 11:12:26AM -0700, Nanley Chery wrote:
> > On Mon, May 07, 2018 at 03:36:54PM +0300, Pohjolainen, Topi wrote:
> > > On Thu, May 03, 2018 at 12:03:55PM -0700, Nanley Chery wrote:
> > > > We're going to delete
On Mon, May 07, 2018 at 11:35:39AM -0700, Nanley Chery wrote:
> On Mon, May 07, 2018 at 10:10:16AM -0700, Nanley Chery wrote:
> > On Mon, May 07, 2018 at 11:51:50AM +0300, Pohjolainen, Topi wrote:
> > > On Fri, May 04, 2018 at 11:04:40AM -0700, Nanley Chery wrote:
> > > > On Fri, May 04, 2018 at
When VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT is set we skip NIR
linking optimisations and only run over the NIR optimisation loop
once similar to the GLSLOptimizeConservatively constant used by
some GL drivers.
We need to run over the opts at least once to avoid errors in LLVM
(e.g. dead vars
On Mon, May 7, 2018 at 8:02 PM, Brian Paul wrote:
>
> I don't know when this started happening (I'll try bisecting tomorrow) but
> we're seeing a crash in ast_type_qualifier::validate_in_qualifier() in -O3
> builds with gcc 5.4.0 on Ubuntu 16.04.
>
> Specifically, at
Mesa 18.0.1 can hang on Raven. It's fixed in Mesa 18.0.2.
Marek
On Thu, May 3, 2018 at 10:29 PM, Jerry DeLisle
wrote:
> Hi folks,
>
> I search a thread earlier that identified that someone could reproduce
> this problem.
>
> I don't have skills or tools to debug this,
CC:
Signed-off-by: Jan Vesely
---
src/gallium/drivers/r600/evergreen_compute.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index
Reviewed-by: Marek Olšák
Marek
On Sun, May 6, 2018 at 5:40 AM, Alejandro Piñeiro
wrote:
> is_resource_supported returns if the combination of
> target/internalformat is supported in at least one operation. Online
> compression is only mandatory for
CC:
Signed-off-by: Jan Vesely
---
src/gallium/drivers/r600/r600_pipe.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index
I don't know when this started happening (I'll try bisecting tomorrow)
but we're seeing a crash in ast_type_qualifier::validate_in_qualifier()
in -O3 builds with gcc 5.4.0 on Ubuntu 16.04.
Specifically, at ast_type.cpp:654:
if ((this->flags.i & ~valid_in_mask.flags.i) != 0) {
It seems
On Thu, May 3, 2018 at 12:29 PM, Gert Wollny
wrote:
> Am Donnerstag, den 03.05.2018, 11:43 -0400 schrieb Ilia Mirkin:
> > You're supposed to keep track of the bound state (usually in the
> > context). After your clear() implementation is done, you have to undo
> > all
In vrend_clear, we already save and restore colormasks and stencils:
https://cgit.freedesktop.org/virglrenderer/commit/?id=b75e0a1dabdfbda44c310a69026a9dbd7d980294
https://cgit.freedesktop.org/virglrenderer/commit/?id=252b00d77c30ce39608c1a9de18523cbdcaca623
It would be nice if we can put
On 08/05/18 10:49, Timothy Arceri wrote:
This allows drivers to define what version of GLSL they support
in compat. This will be needed in order to support comapat 3.2
without breaking driver that wont support it.
This also fixes MESA_GLSL_VERSION_OVERRIDE for compat.
Sorry no it doesn't fix
Just let validate_context_version() do it instead. This fixes
MESA_GL_VERSION_OVERRIDE for compat, it will also allow us to
enable new compat versions on a per driver bases in future.
---
src/mesa/drivers/dri/common/dri_util.c | 8
1 file changed, 8 deletions(-)
diff --git
This allows drivers to define what version of GLSL they support
in compat. This will be needed in order to support comapat 3.2
without breaking driver that wont support it.
This also fixes MESA_GLSL_VERSION_OVERRIDE for compat.
---
src/mesa/drivers/dri/i915/intel_extensions.c | 1 +
Just leave it as 0 and let the drivers set it (as they already do)
to avoid redundantly initialising it.
---
src/mesa/main/context.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 9a4bf8d3942..9bd4661bd86 100644
---
All drivers that support GLSL will later set their default GLSL versions
overriding this override call. They currently all call
_mesa_override_glsl_version() again later in order to support overrides.
---
src/mesa/main/context.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
From: Jason Ekstrand
This is simple linear-walk first-fit allocator roughly based on the
allocator in the radeon winsys code. This allocator has two primary
functional differences:
1) It cleanly returns 0 on allocation failure
2) It allocates addresses top-down
These will be used to assign virtual addresses to soft pinned
buffers in a later patch.
Two allocators are added for separate 'low' and 'high' virtual
memory areas. Another alternative would have been to add a
double-sided allocator, which wasn't done here just because it
didn't appear to give
---
src/intel/vulkan/anv_allocator.c | 16 +++-
src/intel/vulkan/anv_batch_chain.c | 27 +--
src/intel/vulkan/anv_device.c | 32
src/intel/vulkan/anv_private.h | 16
src/intel/vulkan/anv_queue.c
The state_pools reserve virtual address space of the full
BLOCK_POOL_MEMFD_SIZE, but maintain the current behavior of
growing from the middle.
v2: - rename block_pool::offset to block_pool::start_address (Jason)
- assign state pool start_address statically (Jason)
---
References to pinned bos won't need relocated, so just write the
final value of the reference into the bo. Add a `set` to the
relocation lists for tracking dependencies that were previously
tracked by relocations.
v2: - visit bos from the dependency set in a deterministic order (Jason)
---
A later patch will make use of this in other places. Also, remove
dependency on undefined behavior of left-shifting a signed value.
---
src/intel/vulkan/anv_batch_chain.c | 12 +---
src/intel/vulkan/anv_private.h | 15 +++
2 files changed, 16 insertions(+), 11 deletions(-)
Soft pinning lets us satisfy the binding table address
requirements without using both sides of a growing state_pool.
If you do use both sides of a state pool, then you need to read
the state pool's center_bo_offset (with the device mutex held) to
know the final offset of relocations that target
The test pseudo-randomly makes allocations and deallocations with
the virtual memory allocator and checks that the results are
consistent. Specifically, we test that:
* no result from the allocator overlaps an already allocated range
* allocated memory fulfills the stated alignment requirement
Round two of anv softpin. The only notable feedback not incorporated in
the series is Chris's suggestion about embedding the vma's allocation
node in struct anv_bo; I'm leaving the allocator bit to Jason.
Jason Ekstrand (1):
util: Add a virtual memory allocator
Scott D Phillips (7):
util:
On Mon, May 7, 2018 at 4:05 PM, Scott D Phillips wrote:
> Jason Ekstrand writes:
>
> > If I'm honest, I don't really like the way this patch worked out. It has
> > the virtue of being fairly simple and a nice incremental change.
> However,
> >
From: Roland Scheidegger
We were never producing negative numbers for signed types.
Also fix only producing half the valid range for uint32, and
properly clamp signed values.
Because this now also properly tests snorm with actually negative
values, need to increase eps for
Jason Ekstrand writes:
> If I'm honest, I don't really like the way this patch worked out. It has
> the virtue of being fairly simple and a nice incremental change. However,
> it seems to me like we should be able to do better. That said, I don't
> really know how
On Thursday, May 3, 2018 11:51:52 PM PDT Chris Wilson wrote:
> Quoting Kenneth Graunke (2018-05-04 02:12:39)
> > ---
> > src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > This enables it for Broadwell (with a 64-bit kernel) and Skylake+
On Saturday, May 5, 2018 12:25:20 AM PDT Chris Wilson wrote:
> Quoting Kenneth Graunke (2018-05-04 02:12:36)
[snip]
> > +static uint64_t
> > +bucket_vma_alloc(struct brw_bufmgr *bufmgr,
> > + struct bo_cache_bucket *bucket,
> > + enum brw_memory_zone memzone)
> > +{
On 05/04/2018 03:27 PM, Rhys Perry wrote:
> CC:
> Signed-off-by: Rhys Perry
> ---
> src/mesa/main/fbobject.c | 72
> +++-
> 1 file changed, 41 insertions(+), 31 deletions(-)
>
> diff --git
---
src/intel/isl/isl_format.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index a5bbdbc..a5fdf43 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -108,8 +108,8
---
src/intel/isl/isl_storage_image.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/src/intel/isl/isl_storage_image.c
b/src/intel/isl/isl_storage_image.c
index 20f6fd5..ed1c600 100644
--- a/src/intel/isl/isl_storage_image.c
+++
Hello,
On Mon, 7 May 2018 14:07:05 -0700, Matt Turner wrote:
> On Mon, May 7, 2018 at 4:34 AM, Thomas Petazzoni
> wrote:
> > The configure.ac logic added in commit
> > 2ef7f23820a67e958c2252bd81eb0458903ebf33 ("configure: check if
> > -latomic is needed for
Reviewed-by: Jason Ekstrand
On Mon, May 7, 2018 at 1:51 PM, Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:
> Series is
>
> Reviewed-by: Caio Marcelo de Oliveira Filho
>
>
> On Mon, May 07, 2018 at 01:40:44PM -0700, Kenneth
Acked-by: Jason Ekstrand
On Mon, May 7, 2018 at 1:40 PM, Kenneth Graunke
wrote:
> Chris recently fixed a bunch of genxml end < start bugs, as well as
> booleans that are wider than a bit. These are way too easy to write, so
> asserting that the
Reviewed-by: Jason Ekstrand
At one point, I wrote a script for finding these
On Mon, May 7, 2018 at 1:40 PM, Kenneth Graunke
wrote:
> None of these are actually booleans. Tile Parameter is a tiling mode
> enum. Display pipes take plane
On Mon, May 7, 2018 at 4:34 AM, Thomas Petazzoni
wrote:
> The configure.ac logic added in commit
> 2ef7f23820a67e958c2252bd81eb0458903ebf33 ("configure: check if
> -latomic is needed for __atomic_*") makes the assumption that if a
> 64-bit atomic intrinsic test
Series is
Reviewed-by: Caio Marcelo de Oliveira Filho
On Mon, May 07, 2018 at 01:40:44PM -0700, Kenneth Graunke wrote:
> Python's assert can take both a condition and a string, which will cause
> it to print the string if the assertion trips. (You can't use parens as
Chris recently fixed a bunch of genxml end < start bugs, as well as
booleans that are wider than a bit. These are way too easy to write, so
asserting that the fields are sane is a good plan.
---
src/intel/genxml/gen_pack_header.py | 7 +++
1 file changed, 7 insertions(+)
diff --git
None of these are actually booleans. Tile Parameter is a tiling mode
enum. Display pipes take plane numbers. Predicate Enable has some
operations (and the default value of 6 was particular bogus).
---
src/intel/genxml/gen10.xml | 4 ++--
src/intel/genxml/gen11.xml | 10 +-
Python's assert can take both a condition and a string, which will cause
it to print the string if the assertion trips. (You can't use parens as
that creates a tuple.) Doing "condition and string" works in C, but
doesn't have the desired effect in Python.
---
src/intel/genxml/gen_pack_header.py
Now that we're using ISL, a good chunk of brw_emit_depthstencil is
pointless checks which ISL will do for us anyway. Since we only have
one manual depth buffer emit function, move the useful bits into it.
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 107 +++--
1 file
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 90 +-
1 file changed, 40 insertions(+), 50 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index e44baf2..03535f6 100644
---
The only reason why we had two atoms was that the one we used for gen7+
depended on _NEW_DEPTH and _NEW_STENCIL as well as _NEW_BUFFERS. Since
this is no longer true, we can combine them into one atom. We do add a
dependence on BRW_NEW_AUX_STATE but that should never get set on gen4-5
so adding
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 19 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 25 -
2 files changed, 7 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
We leave gen4-5 alone because the ISL code hasn't really been well-
tested on gen4-5 or with combined depth-stencil because we don't use
BLORP for depth operations on gen4-5. Also, the gen4-5 code has to deal
with intratile offsets for LOD hacks and ISL doesn't handle those yet.
We could make ISL
---
src/mesa/drivers/dri/i965/gen6_depth_state.c | 34 ++--
src/mesa/drivers/dri/i965/gen7_misc_state.c | 32 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 28 +++
3 files changed, 47 insertions(+), 47 deletions(-)
diff
---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 1ce7658..1508473 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++
The hardware will AND these fields with the corresponding fields in
DEPTH_STENCIL_STATE so there's no real reason to toggle them on and off
based on state bits. This removes our reliance on the _NEW_DEPTH and
_NEW_STENCIL state bits and better matches what ISL does.
Cc: Kenneth Graunke
On Mon, May 7, 2018 at 2:36 PM, Jason Ekstrand wrote:
> On Mon, May 7, 2018 at 11:02 AM, Rob Clark wrote:
>>
>> On Mon, May 7, 2018 at 11:53 AM, Jason Ekstrand
>> wrote:
>> > On Mon, May 7, 2018 at 8:02 AM, Alejandro Piñeiro
On Sat, 5 May 2018 08:55:24 +0100
Chris Wilson wrote:
> Quoting James Xiong (2018-05-05 01:56:05)
> > From: "Xiong, James"
> >
> > When one of cached buffers is found to be evicted by kernel,
> > most likely the buffers freed earlier than this
On Mon, 2018-05-07 at 15:10 +0200, Nicolai Hähnle wrote:
> On 04.05.2018 08:34, Jan Vesely wrote:
> > The original bug/corruption was by util_unreference_framebuffer_state,
> > trying to drop reference on cbuf[0] (global AS for OCL).
> > Adding reference counting to set_rat uncovered problems with
https://bugs.freedesktop.org/show_bug.cgi?id=106180
--- Comment #17 from mercuriete ---
The patch implemented by Bas
https://patchwork.freedesktop.org/patch/220792/
has been
Tested-by: Abel Garcia Dorta
on top of master
and on top of
On Mon, May 7, 2018 at 9:24 AM, Scott D Phillips wrote:
> Jason Ekstrand writes:
>
> > On Wed, May 2, 2018 at 9:01 AM, Scott D Phillips <
> scott.d.phill...@intel.com
> >> wrote:
> >
> >> These will be used to assign virtual addresses to soft
On Mon, May 7, 2018 at 7:53 AM, Nicolai Hähnle wrote:
> On 02.05.2018 06:13, Marek Olšák wrote:
>
>> From: Marek Olšák
>>
>> This results in better 16x and 8x quality when using these locations.
>> Verified with the piglit MSAA accuracy test.
>>
>
> How
On Mon, May 07, 2018 at 11:12:26AM -0700, Nanley Chery wrote:
> On Mon, May 07, 2018 at 03:36:54PM +0300, Pohjolainen, Topi wrote:
> > On Thu, May 03, 2018 at 12:03:55PM -0700, Nanley Chery wrote:
> > > We're going to delete intel_miptree_alloc_ccs() in the next commit. With
> > > that in mind,
On Mon, May 7, 2018 at 9:37 AM, Kenneth Graunke
wrote:
> On Monday, May 7, 2018 8:53:34 AM PDT Jason Ekstrand wrote:
> > On Mon, May 7, 2018 at 8:02 AM, Alejandro Piñeiro
> > wrote:
> >
> > > Hi Jason,
> > >
> > > as part of the ARB_gl_spirv work, we
On Mon, May 7, 2018 at 11:02 AM, Rob Clark wrote:
> On Mon, May 7, 2018 at 11:53 AM, Jason Ekstrand
> wrote:
> > On Mon, May 7, 2018 at 8:02 AM, Alejandro Piñeiro
> > wrote:
> >>
> >> Hi Jason,
> >>
> >> as part of the
On Mon, May 07, 2018 at 10:10:16AM -0700, Nanley Chery wrote:
> On Mon, May 07, 2018 at 11:51:50AM +0300, Pohjolainen, Topi wrote:
> > On Fri, May 04, 2018 at 11:04:40AM -0700, Nanley Chery wrote:
> > > On Fri, May 04, 2018 at 10:00:32AM -0700, Nanley Chery wrote:
> > > > On Fri, May 04, 2018 at
On Mon, May 7, 2018 at 7:52 AM, Nicolai Hähnle wrote:
> On 02.05.2018 06:13, Marek Olšák wrote:
>
>> From: Marek Olšák
>>
>> Discovered by luck. Verified with the piglit MSAA accuracy test.
>> It also shows that the worst case EQAA 16s4f results in very
On Mon, May 7, 2018 at 7:49 AM, Nicolai Hähnle wrote:
> On 02.05.2018 06:13, Marek Olšák wrote:
>
>> From: Marek Olšák
>>
>> ---
>> src/gallium/drivers/radeonsi/si_state.c | 3 -
>> src/gallium/drivers/radeonsi/si_state_msaa.c | 154
On Mon, May 07, 2018 at 04:12:24PM +0300, Pohjolainen, Topi wrote:
> On Thu, May 03, 2018 at 12:03:56PM -0700, Nanley Chery wrote:
> > There isn't much that changes between the aux allocation functions.
> > Remove the duplicated code.
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c |
On Mon, May 07, 2018 at 03:36:54PM +0300, Pohjolainen, Topi wrote:
> On Thu, May 03, 2018 at 12:03:55PM -0700, Nanley Chery wrote:
> > We're going to delete intel_miptree_alloc_ccs() in the next commit. With
> > that in mind, replace the use of this function in
> > do_single_blorp_clear() with
On Mon, May 07, 2018 at 03:06:29PM +0300, Pohjolainen, Topi wrote:
> On Thu, May 03, 2018 at 12:03:53PM -0700, Nanley Chery wrote:
> > We have enough information to determine the optimal flags internally.
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29
> >
On Mon, May 7, 2018 at 11:53 AM, Jason Ekstrand wrote:
> On Mon, May 7, 2018 at 8:02 AM, Alejandro Piñeiro
> wrote:
>>
>> Hi Jason,
>>
>> as part of the ARB_gl_spirv work, we are doing the linking based on the
>> nir shader that comes from
On Mon, May 7, 2018 at 8:16 AM, Nicolai Hähnle wrote:
> Very nice. We should probably think about exposing this as a more
> generally available performance knob if you're confident enough that it
> works.
>
I'm absolutely confident that it works. I've run a lot of image
On Mon, May 7, 2018 at 8:17 AM, Nicolai Hähnle wrote:
> On 01.05.2018 22:48, Marek Olšák wrote:
>
>> +**nr_color_samples**: This is the number of color samples for
>> EQAA, while
>> +``nr_samples`` is the number of coverage samples. If the format
>>
Thanks.
Reviewed-by: Matt Turner
and pushed.
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On Mon, May 07, 2018 at 11:30:15AM +0300, Pohjolainen, Topi wrote:
> On Thu, May 03, 2018 at 12:03:51PM -0700, Nanley Chery wrote:
> > The indirect clear color isn't correctly tracked in
> > intel_miptree::fast_clear_color. The initial value of ::fast_clear_color
> > is zero, while that of the
On Mon, May 07, 2018 at 11:51:50AM +0300, Pohjolainen, Topi wrote:
> On Fri, May 04, 2018 at 11:04:40AM -0700, Nanley Chery wrote:
> > On Fri, May 04, 2018 at 10:00:32AM -0700, Nanley Chery wrote:
> > > On Fri, May 04, 2018 at 09:42:34AM -0700, Nanley Chery wrote:
> > > > On Thu, May 03, 2018 at
From: Ville Syrjälä
platform_x11 with dri3 needs inc_loader.
In file included from ../src/egl/drivers/dri2/platform_x11_dri3.c:35:0:
../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: No
such file or directory
In file included from
On Sat, 5 May 2018 09:11:28 +0100
Chris Wilson wrote:
> Quoting James Xiong (2018-05-05 01:56:01)
> > This series align the buffer size up to page instead of a bucket
> > size to improve memory allocation efficiency.
>
> It doesn't though. It still retrieves up to
On Mon, May 07, 2018 at 09:49:01AM +0300, Tapani Pälli wrote:
>
> On 05/04/2018 05:59 PM, Nanley Chery wrote:
> > On Fri, May 04, 2018 at 09:03:32AM +0300, Tapani Pälli wrote:
> > > Hi Nanley;
> > >
> >
> > Hey Tapani,
> >
> > > On 05/03/2018 10:03 PM, Nanley Chery wrote:
> > > > Before this
On Monday, May 7, 2018 8:53:34 AM PDT Jason Ekstrand wrote:
> On Mon, May 7, 2018 at 8:02 AM, Alejandro Piñeiro
> wrote:
>
> > Hi Jason,
> >
> > as part of the ARB_gl_spirv work, we are doing the linking based on the
> > nir shader that comes from spirv_to_nir. On some
Reviewed-by: Matt Turner
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We used to only initialize BLORP on Gen6+. When we added it on Gen4-5,
we forgot to destroy it unconditionally.
Fixes: 752d7af77a52898cebf5597def4fdd38b1d6303e (i965: Add blorp support for
gen4-5)
---
src/mesa/drivers/dri/i965/brw_context.c | 3 +--
1 file changed, 1 insertion(+), 2
Quoting Gert Wollny (2018-04-28 12:30:08)
> v2: Define tests also in the meson.build file.
> Signed-off-by: Gert Wollny
> ---
> src/mesa/state_tracker/tests/Makefile.am | 20 +-
> src/mesa/state_tracker/tests/meson.build | 14 +
>
Jason Ekstrand writes:
> On Wed, May 2, 2018 at 9:01 AM, Scott D Phillips > wrote:
>
>> These will be used to assign virtual addresses to soft pinned
>> buffers in a later patch.
>> ---
>> src/intel/vulkan/anv_device.c | 75
Quoting Dylan Baker (2018-05-06 12:38:54)
>
>
> On May 4, 2018 5:44:25 PM PDT, Chad Versace wrote:
> >
> >The BUG line should be converted to any of the following trailer lines:
> >
> >Bug: https://crbug.com/776903
> >(This is my favorite).
> >Fixes:
On Saturday, May 5, 2018 12:49:18 AM PDT Chris Wilson wrote:
> Quoting Chris Wilson (2018-05-04 22:27:27)
> > Quoting Kenneth Graunke (2018-05-04 02:12:36)
> > > + if (brw_using_softpin(bufmgr) && bo->gtt_offset == 0ull) {
> > > + bo->gtt_offset = vma_alloc(bufmgr, memzone, bo->size, 1);
>
On Friday, May 4, 2018 2:27:27 PM PDT Chris Wilson wrote:
> Quoting Kenneth Graunke (2018-05-04 02:12:36)
> > + if (brw_using_softpin(bufmgr) && bo->gtt_offset == 0ull) {
> > + bo->gtt_offset = vma_alloc(bufmgr, memzone, bo->size, 1);
> > +
> > + if (bo->gtt_offset == 0ull)
> > +
On Friday, May 4, 2018 2:18:11 PM PDT Chris Wilson wrote:
> Quoting Kenneth Graunke (2018-05-04 02:12:35)
> > diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > index 66f30a1637f..66828f319be 100644
> > --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
Acked-by: Jason Ekstrand
On Mon, May 7, 2018 at 8:45 AM, Kenneth Graunke
wrote:
> Gen4-5 traditionally don't use GEM context support, which means that
> the PS_DEPTH_COUNT register isn't saved/restored for us across batches.
>
> This means that we
On Mon, May 7, 2018 at 8:02 AM, Alejandro Piñeiro
wrote:
> Hi Jason,
>
> as part of the ARB_gl_spirv work, we are doing the linking based on the
> nir shader that comes from spirv_to_nir. On some cases,
> nir_lower_wpos_ytransform introduces a new uniform,
>
Gen4-5 traditionally don't use GEM context support, which means that
the PS_DEPTH_COUNT register isn't saved/restored for us across batches.
This means that we have to bookend each batch with start/end snapshots,
and add deltas from a series of pairs, instead of simply having a single
A bunch of nit-picks below.
On 05/04/2018 06:09 AM, Rhys Perry wrote:
Signed-off-by: Rhys Perry
---
src/mapi/glapi/gen/gl_API.xml | 52 +++
src/mesa/main/config.h | 7 +
src/mesa/main/dd.h | 7 +
On 05/04/2018 06:09 AM, Rhys Perry wrote:
Signed-off-by: Rhys Perry
---
src/gallium/auxiliary/cso_cache/cso_context.c| 31 +++
src/gallium/auxiliary/cso_cache/cso_context.h| 5
src/gallium/auxiliary/util/u_framebuffer.c | 32
More nit-picks below.
On 05/04/2018 06:09 AM, Rhys Perry wrote:
Signed-off-by: Rhys Perry
---
src/mesa/state_tracker/st_atom_framebuffer.c | 64
src/mesa/state_tracker/st_cb_msaa.c | 22 ++
Hi,
On 05.05.2018 03:56, James Xiong wrote:
From: "Xiong, James"
With the current implementation, brw_bufmgr may round up a request
size to the next bucket size, result in 25% more memory allocated in
the worst senario. For example:
Request sizeActual size
Jan Vesely wrote on 02.05.2018 22:38:
> On Wed, 2018-05-02 at 18:38 +0200, Kai Wasserbäch wrote:
>> [...]
>
> Thank for looking into this. We probably need CLANG_LIBS handling
> similar to LLVM_LIBS. I agree this is the best fix for now.
>
> Acked-by: Jan Vesely
>
>
Reviewed-by: Jason Ekstrand
Have you audited to ensure that we don't actually use it in this case?
On Mon, May 7, 2018 at 1:01 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> According to Vulkan spec:
>
> "pColorBlendState is a pointer to an instance of
On 04.05.2018 20:32, Daniel Schürmann wrote:
This functionality is currently disabled due to a bug in LLVM.
The idea of this implementation is taken from the ROCm Device Libs:
https://github.com/RadeonOpenCompute/ROCm-Device-Libs/blob/master/ockl/src/wfredscan.cl
---
On 05/07/2018 09:14 AM, Christian König wrote:
Am 07.05.2018 um 15:03 schrieb Leo Liu:
On 05/07/2018 05:10 AM, Christian König wrote:
Am 02.05.2018 um 16:51 schrieb Leo Liu:
mpv now interop with video surface instead of output surface
previously,
so it fails with
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