[Mesa-dev] [PATCH 11/14] radeonsi: Enable dynamic HS.

This allows running the TES on different CU's than the TCS which results in performance improvements. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_shader.c| 11 --- src/gallium/drivers/radeonsi/si_state_shaders.c | 2 +- 2

[Mesa-dev] [PATCH 01/14] radeonsi: Add buffer for offchip storage between TCS and TES.

The buffer is quite large, but should only be allocated if the application uses tessellation. Most non-games don't. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_pipe.c | 1 + src/gallium/drivers/radeonsi/si_pipe.h | 1

[Mesa-dev] [PATCH 08/14] radeonsi: Store inputs to memory when not using a TCS.

, or complexity to avoid that. The main body of the fixed function TCS is not that interesting to precompile anyway, since we do it on demand and it is very small. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_shader.c| 45

[Mesa-dev] [PATCH 03/14] radeonsi: Define build_tbuffer_store_dwords earlier to support new users.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_shader.c | 138 +++ 1 file changed, 69 insertions(+), 69 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_sh

Re: [Mesa-dev] [PATCH] gallium/util: fix undefined shift to the last bit in u_bit_scan

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Sat, Apr 16, 2016 at 2:13 AM, Marek Olšák <mar...@gmail.com> wrote: > From: Marek Olšák <marek.ol...@amd.com> > > --- > src/gallium/auxiliary/util/u_math.h | 2 +- > 1 file changed, 1 insertion(+), 1

Re: [Mesa-dev] [PATCH] gallium/util: fix u_bit_scan_consecutive_range for mask == 0xffffffff

t; *start)) - 1; > *mask &= ~(((1 << *count) - 1) << *start); This signed shift needs to be fixed for *count == 31 too. Either way, Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> > -- > 2.5.0 > > ___

[Mesa-dev] [PATCH v4] radeonsi: enable TGSI support cap for compute shaders

v2: Use chip_class instead of family. v3: Check kernel version for SI. v4: Preemptively allow amdgpu winsys for SI. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- docs/GL3.txt | 4 ++-- docs/relnotes/11.3.0.html | 1

Re: [Mesa-dev] [PATCH] radeonsi: enable GLSL 4.30 and therefore OpenGL 4.3

On Mon, Apr 18, 2016 at 7:58 PM, Ian Romanick wrote: > On 04/15/2016 03:33 AM, Marek Olšák wrote: >> The same thing Nicolai said: This can be committed before the UE4 >> compile failure is fixed. > > Is there a bug filed for that problem? Has anyone diagnosed the issue? >

Re: [Mesa-dev] [PATCH v3 2/2] radeonsi: enable TGSI support cap for compute shaders

On Tue, Apr 19, 2016 at 4:03 PM, Alex Deucher <alexdeuc...@gmail.com> wrote: > On Tue, Apr 19, 2016 at 6:56 AM, Marek Olšák <mar...@gmail.com> wrote: >> Reviewed-by: Marek Olšák <marek.ol...@amd.com> >> >> Marek >> >> On Tue, Apr 19, 2016 at 1:39

[Mesa-dev] [PATCH v2 04/12] winsys/amdgpu: Enlarge const IB size.

Necessary to prevent performance regressions due to extra flushing. Probably should enlarge it even further when also updating uniforms through the CE, but this seems large enough for now. v2: Add preamble IB. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/

[Mesa-dev] [PATCH v2 08/12] radeonsi: Allocate chunks of CE ram.

v2: Use 32 byte alignment. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 30 +++ src/gallium/drivers/radeonsi/si_state.h | 3 +++ 2 files changed, 24 insertions(+), 9 deletions(-) diff --git

[Mesa-dev] [PATCH v2 03/12] winsys/amdgpu: Add support for const IB.

From: Marek Olšák <marek.ol...@amd.com> v2: Use the correct IB to update request (Bas Nieuwenhuizen) v3: Add preamble IB. (Bas Nieuwenhuizen) --- src/gallium/drivers/radeon/radeon_winsys.h | 30 ++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 88 -

[Mesa-dev] [PATCH v2 07/12] radeonsi: Add CE synchronization.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_state_draw.c | 24 2 files changed, 25 insertions(+) diff

[Mesa-dev] [PATCH v2 02/12] winsys/amdgpu: split IB data into a new structure in preparation for CE

From: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5 --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 6 +++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 68 +++-

[Mesa-dev] [PATCH v2 10/12] radeonsi: Replace list_dirty with a mask.

We can then upload only the dirty ones with the constant engine. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 37 --- src/gallium/drivers/radeonsi/si_state.h | 9 +-- 2 files chang

[Mesa-dev] [PATCH v2 01/12] gallium/radeon: move ring_type into winsyses

From: Marek Olšák <marek.ol...@amd.com> Not used by drivers. Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/radeon_winsys.h| 1 - src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 8 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h

[Mesa-dev] [PATCH v2 05/12] radeonsi: Create CE IB.

Based on work by Marek Olšák. v2: Add preamble IB. Leaves the load packet in the space calculation as the radeon winsys might not be able to support a premable. The added space calculation may look expensive, but is converted to a constant with (at least) -O2 and -O3. Signed-off-by: Bas

[Mesa-dev] [PATCH v2 12/12] radeonsi: Use CE for all descriptors.

v2: Load previous list for new CS instead of re-emitting all descriptors. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 70 +++ 1 file changed, 60 insertions(+), 10 deletions(-) diff --git

[Mesa-dev] [PATCH v2 11/12] gallium/util: Add u_bit_scan_consecutive_range64.

For use by radeonsi. v2: Make sure that it works for all 64 bits set. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/auxiliary/util/u_math.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/auxiliary/util/u_math.h b/src/g

[Mesa-dev] [PATCH v2 00/12] Use the constant engine in radeonsi

think it is not useful to add it already. - Fix u_bit_scan_consecutive_range64 for *mask = ~0llu. - Minor whitespace fixes. Bas Nieuwenhuizen (9): winsys/amdgpu: Enlarge const IB size. radeonsi: Create CE IB. radeonsi: Add CE packet definitions. radeonsi: Add CE synchronization. radeonsi

[Mesa-dev] [PATCH v2 09/12] radeonsi: Add CE uploader.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_descriptors.c | 23 +++ src/gallium/drivers/radeonsi/si_pipe.c| 11 +++ src/gallium/drivers/radeon

[Mesa-dev] [PATCH v2 06/12] radeonsi: Add CE packet definitions.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/sid.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h i

Re: [Mesa-dev] [PATCH v2 05/12] radeonsi: Create CE IB.

On Mon, Apr 18, 2016 at 12:04 AM, Marek Olšák <mar...@gmail.com> wrote: > On Sun, Apr 17, 2016 at 1:43 AM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> Based on work by Marek Olšák. >> >> v2: Add preamble IB. >> >> Leaves the load packet

Re: [Mesa-dev] [PATCH v2 08/12] radeonsi: Allocate chunks of CE ram.

On Mon, Apr 18, 2016 at 12:13 AM, Marek Olšák <mar...@gmail.com> wrote: > On Sun, Apr 17, 2016 at 1:43 AM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> v2: Use 32 byte alignment. >> >> Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl&g

Re: [Mesa-dev] [PATCH 1/4] radeonsi: use CE suballocator for CP DMA realignment.

I retract patch 1 and 2. Large scratch buffers are nice, but the hardware only supports a 32-bit offset into it. - Bas On Wed, Apr 20, 2016 at 12:50 AM, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote: > Use the CE suballocator instead of the normal one as the usage > is

[Mesa-dev] [PATCH 3/4] radeonsi: Prevent overflow when calculating the scratch size.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c | 5 - src/gallium/drivers/radeonsi/si_state_shaders.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c

[Mesa-dev] [PATCH 2/4] radeonsi: Use winsys pb_buffer for scratch buffers.

Allows allocation of >= 4 GiB. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c | 23 +++ src/gallium/drivers/radeonsi/si_pipe.c | 4 ++-- src/gallium/drivers/radeonsi/si_pipe.h | 4

[Mesa-dev] [PATCH 1/4] radeonsi: use CE suballocator for CP DMA realignment.

Use the CE suballocator instead of the normal one as the usage is most similar to the CE, i.e. only read and written on GPU and not mapped to CPU. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_cp_dma.c | 27 ++-

[Mesa-dev] [PATCH 4/4] radeonsi: Print a message when scratch allocation fails.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c | 5 - src/gallium/drivers/radeonsi/si_state_shaders.c | 5 - 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c

Re: [Mesa-dev] [PATCH 2/2] winsys/amdgpu: clean up and fix switch statement

On Wed, Apr 20, 2016 at 1:13 AM, Grigori Goronzy wrote: > Add missing break, add default case. Additionally initialize variables > to avoid compiler warnings. > --- > src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > >

Re: [Mesa-dev] [PATCH 1/4] radeonsi: use CE suballocator for CP DMA realignment.

On Wed, Apr 20, 2016 at 2:13 AM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > On 19.04.2016 18:29, Bas Nieuwenhuizen wrote: >> >> I retract patch 1 and 2. Large scratch buffers are nice, but the >> hardware only supports a 32-bit offset into it. > > > Do

[Mesa-dev] [PATCH] glsl: Use correct mode for split components.

The mode should stay the same as the original struct. In particular, shared should not be changed to temporary. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/compiler/glsl/opt_structure_splitting.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH] st/mesa: Use correct size for compute CAPs.

Some CAPs are stored as 64-bit value while Mesa stores the related constant as 32-bit value. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/mesa/state_tracker/st_extensions.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mesa/state_t

[Mesa-dev] [PATCH v2 09/20] radeonsi: don't pass scratch buffer to user SGPRs

As far as I can see we use relocations for clover too. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/gallium/drivers/radeonsi/si_compute.c | 8

[Mesa-dev] [PATCH v2 01/20] radeonsi: lower compute shader arguments

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/gallium/drivers/radeonsi/si_shader.c | 41 src/gallium/drivers/radeons

[Mesa-dev] [PATCH v2 10/20] radeonsi: do per cs setup for compute shaders once per cs

Also removes PKT3_CONTEXT_CONTROL as that is already being done by si_begin_new_cs, when emitting init_config. v2: - Use radeon_set_sh_reg_seq. - Also set COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 for CIK+ Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Nicolai

[Mesa-dev] [PATCH v2 06/20] radeonsi: update shader count for compute shaders

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/gallium/drivers/radeonsi/si_state.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/s

[Mesa-dev] [PATCH v2 15/20] radeonsi: split texture decompression for compute shaders

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/gallium/drivers/radeonsi/si_blit.c | 13 +++-- src/gallium/drivers/radeonsi/si_compute.c|

[Mesa-dev] [PATCH v2 02/20] radeonsi: add shared memory

Declares the shared memory as a global variable so that LLVM is aware of it and it does not conflict with passes like AMDGPUPromoteAlloca. v2: - Use ctx->i8. - Dropped null-check for declare_memory_region. - Changed memory region array to single region. Signed-off-by: Bas Nieuwenhui

[Mesa-dev] [PATCH 1/2] winsys/amdgpu: Silence possibly uninitialized variable warning.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index bbd29fc..69fb9bb 100644 --- a/src/g

[Mesa-dev] [PATCH 2/2] gallium/radeon: Silence possibly uninitialized variable warning.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/radeon_llvm_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c b/src/gallium/drivers/radeon/radeon_llvm_emit.c index 7174132..d

Re: [Mesa-dev] [PATCH 02/10] radeonsi: make RW buffer descriptor array global, not per shader stage

On Wed, Apr 20, 2016 at 5:47 PM, Marek Olšák wrote: > From: Marek Olšák > > --- > src/gallium/drivers/radeonsi/si_descriptors.c | 50 > +-- > src/gallium/drivers/radeonsi/si_pipe.h| 2 +- > 2 files changed, 25

[Mesa-dev] [PATCH 1/2] radeonsi: Use defines for CONTEXT_CONTROL instead of magic values.

I have no source for the actual name of these fields, as these are not in the kernel headers. I hope they are clear though. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_state.c | 4 ++-- src/gallium/drivers/radeonsi/sid.h | 3 +++ 2

Re: [Mesa-dev] [PATCH 4/4] radeonsi: Print a message when scratch allocation fails.

On Wed, Apr 20, 2016 at 8:33 AM, <eocallag...@alterapraxis.com> wrote: > On 2016-04-20 11:46, Nicolai Hähnle wrote: >> >> On 19.04.2016 17:50, Bas Nieuwenhuizen wrote: >>> >>> Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> >>&g

Re: [Mesa-dev] [PATCH 00/10] RadeonSI: cleanup RW shader slots

> RW buffer descriptors are made global, not per shader stage, so all shaders > receive the same pointer. > > Finally, all shader resource binding masks are shortened to 32 bits. > > Please review. Except for patch 2, which I've commented on, the series is Reviewed-by: Bas Nieuw

[Mesa-dev] [PATCH 1/3] gallium/ddebug: Add passthrough for get_compute_param.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/ddebug/dd_screen.c | 12 1 file changed, 12 insertions(+) diff --git a/src/gallium/drivers/ddebug/dd_screen.c b/src/gallium/drivers/ddebug/dd_screen.c index fbc0bec..ebe090b 100644 --- a/src/g

[Mesa-dev] [PATCH 3/3] gallium/ddebug: Implement launch_grid.

Does not implement dumping info. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/ddebug/dd_draw.c | 29 + 1 file changed, 29 insertions(+) diff --git a/src/gallium/drivers/ddebug/dd_draw.c b/src/gallium/drivers/ddebug/dd_

[Mesa-dev] [PATCH 2/3] gallium/ddebug: Support compute states.

Note that compute states have a different struct than the other shader states, so we cannot reuse the macro. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/ddebug/dd_context.c | 37 + 1 file changed, 37 insertions(+)

[Mesa-dev] [PATCH v3 09/12] radeonsi: Add CE uploader.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_descriptors.c | 23 +++ src/gallium/drivers/radeonsi/si_pipe.c| 11 +++ src/gallium/drivers/radeon

[Mesa-dev] [PATCH v3 05/12] radeonsi: Create CE IB.

. - Remove needed space for vertex buffer descriptors. - Fail when the preamble cannot be created. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_pipe_common.c | 1 + src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/d

[Mesa-dev] [PATCH v3 01/12] gallium/radeon: move ring_type into winsyses

From: Marek Olšák <marek.ol...@amd.com> Not used by drivers. Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/radeon_winsys.h| 1 - src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 8 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h

[Mesa-dev] [PATCH v3 10/12] radeonsi: Replace list_dirty with a mask.

We can then upload only the dirty ones with the constant engine. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_descriptors.c | 37 --- src/gallium/drivers/radeons

[Mesa-dev] [PATCH v3 07/12] radeonsi: Add CE synchronization.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_state_draw.c | 24 2 files changed, 25 insertions(+) diff

[Mesa-dev] [PATCH v3 08/12] radeonsi: Allocate chunks of CE ram.

v2: Use 32 byte alignment. v3: Don't allocate CE space for vertex buffer descriptors. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 33 +++ src/gallium/drivers/radeonsi/si_state.h | 3 +++ 2

[Mesa-dev] [PATCH v3 03/12] winsys/amdgpu: Add support for const IB.

From: Marek Olšák <marek.ol...@amd.com> v2: Use the correct IB to update request (Bas Nieuwenhuizen) v3: Add preamble IB. (Bas Nieuwenhuizen) Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeon/radeon_winsys.h | 30 ++ src/gallium/winsys/amdgpu/drm

[Mesa-dev] [PATCH v3 02/12] winsys/amdgpu: split IB data into a new structure in preparation for CE

From: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5 --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 6 +++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 68 +++-

[Mesa-dev] [PATCH v3 06/12] radeonsi: Add CE packet definitions.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/sid.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h i

[Mesa-dev] [PATCH v3 04/12] winsys/amdgpu: Enlarge const IB size.

Necessary to prevent performance regressions due to extra flushing. Probably should enlarge it even further when also updating uniforms through the CE, but this seems large enough for now. v2: Add preamble IB. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek

[Mesa-dev] [PATCH v3 00/12] Constant engine for radeonsi

Changes from v2: - Remains of vertex buffer descriptor support have been removed. Both wrt the space calculation and allocating CE ram. - Failing to create a preamble IB now rersults in failure. - Misc style fixes in patch 5 and 12. - Bas Bas Nieuwenhuizen (9): winsys/amdgpu

[Mesa-dev] [PATCH v3 12/12] radeonsi: Use CE for all descriptors.

v2: Load previous list for new CS instead of re-emitting all descriptors. v3: Do radeon_add_to_buffer_list in si_ce_upload. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_descri

[Mesa-dev] [PATCH v3 11/12] gallium/util: Add u_bit_scan_consecutive_range64.

For use by radeonsi. v2: Make sure that it works for all 64 bits set. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/auxiliary/util/u_math.h | 14 ++ 1 file changed, 14 insertions(+) diff

[Mesa-dev] [PATCH v3 12/12] radeonsi: Use CE for all descriptors.

v2: Load previous list for new CS instead of re-emitting all descriptors. v3: Do radeon_add_to_buffer_list in si_ce_upload. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- Forgot to save the file before amendi

[Mesa-dev] [PATCH v3 0/2] Remainder radeonsi compute patches.

updated the update cap patch, as I discovered that writing the USER_DATA registers from a COPY_DATA packet was disallowed by the kernel with the SI CS checker. Now that that has been fixed in the kernel, the new patch checks for the drm version that has the fix. Bas Nieuwenhuizen (2): radeonsi

[Mesa-dev] [PATCH v3 2/2] radeonsi: enable TGSI support cap for compute shaders

v2: Use chip_class instead of family. v3: Check kernel version for SI. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- docs/GL3.txt | 4 ++-- docs/relnotes/11.3.0.html | 1 + src/gallium/drivers/radeon/r600_pipe_co

[Mesa-dev] [PATCH v3 1/2] radeonsi: do not do two full flushes on every compute dispatch

CS_PARTIAL_FLUSH events even if we already have INV_GLOBAL_L2. According to Marek the INV_GLOBAL_L2 events don't wait for compute shaders to finish, so wait for them explicitly. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c

Re: [Mesa-dev] [PATCH v3 1/2] radeonsi: do not do two full flushes on every compute dispatch

n be read-after-write hazards when transitioning from compute > to graphics and vice versa. Is the user expected to call > glMemoryBarrier in this case or do we need to synchronize explicitly > in the driver? > > Marek > > On Tue, Apr 19, 2016 at 1:39 AM, Bas Nieuwenhuizen >

[Mesa-dev] [PATCH 2/2] radeonsi: Consider input SGPR count for compute shader SGPR count.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c | 16 +++- src/gallium/drivers/radeonsi/si_shader.c | 3 ++- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c

[Mesa-dev] [PATCH 1/2] radeonsi: Add CE synchronization for compute dispatches.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c| 4 src/gallium/drivers/radeonsi/si_state.h | 2 ++ src/gallium/drivers/radeonsi/si_state_draw.c | 4 ++-- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH v2 08/20] radeonsi: split input upload off from si_launch_grid

input_size is 0, as it contains grid parameters. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c | 93 +-- 1 file changed, 52 insertions(+), 41 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c

[Mesa-dev] [PATCH v2 16/20] radeonsi: split setting graphics and compute descriptors

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/gallium/drivers/radeonsi/si_compute.c | 3 ++ src/gallium/drivers/radeonsi/si_

[Mesa-dev] [PATCH v2 19/20] mesa/st: enable compute shaders if images are also supported

v2: Also depend on atomic counters. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/mesa/state_tracker/st_extensions.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mesa/s

[Mesa-dev] [PATCH v2 18/20] radeonsi: clean up compute flush

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/gallium/drivers/radeonsi/si_pipe.h | 3 --- src/gallium/drivers/radeonsi/si

[Mesa-dev] [PATCH v2 04/20] radeonsi: implement shared atomics

v2: - Use single region - Use get_memory_ptr Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_shader.c | 77 +++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_sh

[Mesa-dev] [PATCH v2 03/20] radeonsi: implement shared memory load/store

v2: - Use single region - Combine address calculation Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_shader.c | 84 +++- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/ra

[Mesa-dev] [PATCH v2 07/20] radeonsi: implement TGSI compute shader creation

v2: Moved scratch_enabled initialization after compile. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c | 74 +++ 1 file changed, 56 insertions(+), 18 deletions(-) diff --git a/src/gallium/drivers/ra

[Mesa-dev] [PATCH v2 17/20] radeonsi: do not do two full flushes on every compute dispatch

-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c | 17 ++--- src/gallium/drivers/radeonsi/si_cp_dma.c | 6 -- src/gallium/drivers/radeonsi/si_descriptors.c | 3 ++- src/gallium/drivers/radeonsi/si_state.c | 6 +++

[Mesa-dev] [PATCH v2 20/20] radeonsi: enable TGSI support cap for compute shaders

v2: Use chip_class instead of family. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- docs/GL3.txt | 4 ++-- docs/relnotes/11.3.0.html | 1 + src/gallium/dr

[Mesa-dev] [PATCH v2 12/20] radeonsi: only emit compute shader state when switching shaders

v2: - Do check if anything changed earlier - Use emitted_program instead of emitted_bo to prevent shaders with shader->bo = NULL confusing the check - Use radeon_set_sh_reg* Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_

[Mesa-dev] [PATCH v2 13/20] radeonsi: implement TGSI compute dispatch

v2: - Use radeon_set_sh_reg_seq. - Set predicate bit for conditional rendering. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c | 104 ++ 1 file changed, 77 insertions(+), 27 deletions(-) diff --git

[Mesa-dev] [PATCH v2 05/20] radeonsi: set maximum work group size based on block size

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> --- src/gallium/drivers/radeonsi/si_shader.c | 12 1 file changed, 12 insertions(+) diff --git a/s

[Mesa-dev] [PATCH v2 11/20] radeonsi: rework compute scratch buffer

Instead of having a scratch buffer per program, have one per context. Also removed the per kernel wave count calculations, but that only helped if the total number of waves in the dispatch was smaller than sctx->scratch_waves. v2: Fix style issue. Signed-off-by: Bas Nieuwenhuizen

[Mesa-dev] [PATCH v2 14/20] radeonsi: update predicate condition for compute dispatches

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_compute.c | 6 ++ src/gallium/drivers/radeonsi/si_pipe.h| 9 + 2 files changed, 15 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/ra

[Mesa-dev] [PATCH 01/13] gallium/radeon: move ring_type into winsyses

From: Marek Olšák Not used by drivers. --- src/gallium/drivers/radeon/radeon_winsys.h| 1 - src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 8 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 1 + src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 10 +-

[Mesa-dev] [PATCH 00/13] Use the constant engine in radeonsi

. Bas Nieuwenhuizen (10): winsys/amdgpu: Enlarge const IB size. radeonsi: Create CE IB. radeonsi: Add dirty_mask to descriptor list. radeonsi: Add CE packet definitions. radeonsi: Add CE synchronization. radeonsi: Allocate chunks of CE ram. radeonsi: Add CE uploader. radeonsi: Use

[Mesa-dev] [PATCH 04/13] winsys/amdgpu: Enlarge const IB size.

Necessary to prevent performance regressions due to extra flushing. Probably should enlarge it even further when also updating uniforms through the CE, but this seems large enough for now. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/winsys/amdgpu/drm/amdgp

[Mesa-dev] [PATCH 10/13] radeonsi: Add CE uploader.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 23 +++ src/gallium/drivers/radeonsi/si_pipe.c| 11 +++ src/gallium/drivers/radeonsi/si_pipe.h| 3 +++ 3 files changed, 37 inse

[Mesa-dev] [PATCH 05/13] radeonsi: Create CE IB.

Based on work by Marek Olšák. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_pipe_common.c | 1 + src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeonsi/si_hw_context.c | 4 +++- src/gallium/drivers/radeonsi/si_

[Mesa-dev] [PATCH 06/13] radeonsi: Add dirty_mask to descriptor list.

We can then upload only the dirty ones with the constant engine. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 23 +++ src/gallium/drivers/radeonsi/si_state.h | 1 + 2 files changed, 24 inse

[Mesa-dev] [PATCH 13/13] radeonsi: Use CE for all descriptors.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 46 +-- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/ra

[Mesa-dev] [PATCH 11/13] radeonsi: Use CE for vertex buffers.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 28 --- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/ra

[Mesa-dev] [PATCH 03/13] winsys/amdgpu: add support for const IB

From: Marek Olšák <marek.ol...@amd.com> v2: use the correct IB to update request (Bas Nieuwenhuizen) --- src/gallium/drivers/radeon/radeon_winsys.h | 18 +++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 48 +++--- src/gallium/winsys/amdgpu/drm/amdgpu_cs.h

[Mesa-dev] [PATCH 09/13] radeonsi: Allocate chunks of CE ram.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 29 ++- src/gallium/drivers/radeonsi/si_pipe.h| 1 - src/gallium/drivers/radeonsi/si_state.h | 3 +++ 3 files changed, 23 insertions(

[Mesa-dev] [PATCH 02/13] winsys/amdgpu: split IB data into a new structure in preparation for CE

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5 --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 6 +++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 68 +++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 16 4 files

[Mesa-dev] [PATCH 07/13] radeonsi: Add CE packet definitions.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/sid.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h index f0aa605..1072e0a 100644 --- a/src/gallium/drivers/ra

[Mesa-dev] [PATCH 12/13] gallium/util: Add u_bit_scan_consecutive_range64.

For use by radeonsi. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/auxiliary/util/u_math.h | 8 1 file changed, 8 insertions(+) diff --git a/src/gallium/auxiliary/util/u_math.h b/src/gallium/auxiliary/util/u_math.h index b4ac0db..3a468e4 100644 ---

[Mesa-dev] [PATCH 08/13] radeonsi: Add CE synchronization.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_pipe.h | 2 ++ src/gallium/drivers/radeonsi/si_state_draw.c | 24 2 files changed, 26 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/g

[Mesa-dev] [PATCH v2 2/2] radeonsi: Enable loading into CE RAM.

We need to enable a bit in the CONTEXT_CONTROL packet for the loads to work. v2: Style issues. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 7 +++ src/gallium/drivers/radeonsi/si_hw_context.c | 5 + src/gallium/d

[Mesa-dev] [PATCH v2 1/2] radeonsi: Use defines for CONTEXT_CONTROL instead of magic values.

v2: Use field names provided by Nicolai. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- Sending this with the changed names, as they seem double to me. Should I just lose the register name, and optionally add a CONTEXT_CONTROL prefix? src/gallium/drivers/radeonsi/si_s

Re: [Mesa-dev] [PATCH 2/2] radeonsi: Enable loading into CE RAM.

, 2016 at 11:44 AM, Marek Olšák <mar...@gmail.com> wrote: > On Thu, Apr 21, 2016 at 1:49 AM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> We need to enable a bit in the CONTEXT_CONTROL packet for the >> loads to work. >> >> Signed-off-by: B

[Mesa-dev] [PATCH 2/2] radeonsi: Enable loading into CE RAM.

We need to enable a bit in the CONTEXT_CONTROL packet for the loads to work. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 6 ++ src/gallium/drivers/radeonsi/si_hw_context.c | 5 + src/gallium/drivers/radeonsi/si_s

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