This is an automated email from Gerrit.
Spencer Oliver (s...@spen-soft.co.uk) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/649
-- gerrit
commit b67dc2fd2f9fd59a6b378a9f937552116c602e3e
Author: Spencer Oliver s...@spen-soft.co.uk
Date: Thu May 17
This is an automated email from Gerrit.
Spencer Oliver (s...@spen-soft.co.uk) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/650
-- gerrit
commit ec7962d72b797729b34c22e088b837e4d7a52bf8
Author: Spencer Oliver s...@spen-soft.co.uk
Date: Thu May 17
On Mon, May 14, 2012 at 1:22 AM, Freddie Chopin freddie_cho...@op.pl wrote:
So is there any agreed schedule? Friday 18th of May?
Yes I would like to ask the same question. Maybe 18-May-2012
is already out.
I think the first question is how many of the open gerrit patch
will need to be
On Mon, May 14, 2012 at 1:24 PM, simonqian.openocd
simonqian.open...@gmail.com wrote:
BTW:
I've updated the SWD speed using my SWD patch, it can be the same speed as
JTAG:
Info : device id = 0x10036414
Info : flash size = 256kbytes
stm32x mass erase complete
Info : Padding image section 0
On 16 May 2012 21:58, Gerd v. Egidy li...@egidy.de wrote:
I will look into the openocd code in the next days and try to make these
changes. But I haven't done any coding in openocd itself yet, so maybe someone
more familiar with the code can lend me a hand.
try the attached test patch, if
ger...@openocd.zylin.com wrote:
Author: Paul Fertser fercer...@gmail.com
Date: Thu May 17 23:38:25 2012 +0400
rtos: support FreeRTOS over stlink
Since stlink is a special case it presents the same CPU core under a
different name, so copy the configuration to account for
On Thu, May 17, 2012 at 09:59:02PM +0200, Peter Stuge wrote:
ger...@openocd.zylin.com wrote:
Author: Paul Fertser fercer...@gmail.com
Date: Thu May 17 23:38:25 2012 +0400
rtos: support FreeRTOS over stlink
Since stlink is a special case it presents the same CPU core
Hi,
try the attached test patch, if this solves your problem then we are
heading in the right direction.
Thank you. Yes, it solves the problem - as in I can't reproduce it anymore.
I can still see the SWCLK/SWD wiggle on the logic analyzer before the reset
kicks in. From looking at the code
