On Tue, Aug 2, 2011 at 9:52 AM, Michael Sokolov <msoko...@ivan.harhan.org> wrote:
> Fixing a logic mistake in an FPGA involves editing a Verilog source file > and recompiling; fixing a logic mistake in discrete logic involves a > board respin. I much prefer editing ASCII text source files and > recompiling over respinning PCBs. Yes, compared to a PCB FPGA's are easy to change. But all you need is software, most of which already exists. NTP software can keep system time within a few milliseconds of UTC. No custom hardware, no FPGA or PCB. And this software is already in common use. The only remaining task is to convert UTC to this new kind of time. You don't need an FPGA to do a time conversion. If the requirement were for nano second level accuracy then you need the hardware but software using Internet pool servers is OK for Milliseconds and NTP with a local GPS receiver can do micro seconds. > > MS > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > -- Chris Albertson Redondo Beach, California _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
