Refactor golden registers initialization to take the SDMA engine instance ID as an argument and only program the golden registers for one SDMA engine at once.
Signed-off-by: Timur Kristóf <[email protected]> --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 182 +++++++++++++++++-------- 1 file changed, 127 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 3d0f94372e04..4e6fa9db9948 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -76,13 +76,15 @@ static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = SDMA1_REGISTER_OFFSET }; -static const u32 golden_settings_tonga_a11[] = -{ +static const u32 golden_settings_tonga_a11_sdma0[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, +}; + +static const u32 golden_settings_tonga_a11_sdma1[] = { mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, @@ -90,37 +92,45 @@ static const u32 golden_settings_tonga_a11[] = mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; -static const u32 tonga_mgcg_cgcg_init[] = -{ +static const u32 tonga_mgcg_cgcg_init_sdma0[] = { mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, - mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; -static const u32 golden_settings_fiji_a10[] = -{ +static const u32 tonga_mgcg_cgcg_init_sdma1[] = { + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100, +}; + +static const u32 golden_settings_fiji_a10_sdma0[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, +}; + +static const u32 golden_settings_fiji_a10_sdma1[] = { mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; -static const u32 fiji_mgcg_cgcg_init[] = -{ +static const u32 fiji_mgcg_cgcg_init_sdma0[] = { mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, - mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; -static const u32 golden_settings_polaris11_a11[] = -{ +static const u32 fiji_mgcg_cgcg_init_sdma1[] = { + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100, +}; + +static const u32 golden_settings_polaris11_a11_sdma0[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, +}; + +static const u32 golden_settings_polaris11_a11_sdma1[] = { mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, @@ -128,13 +138,15 @@ static const u32 golden_settings_polaris11_a11[] = mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; -static const u32 golden_settings_polaris10_a11[] = -{ +static const u32 golden_settings_polaris10_a11_sdma0[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, +}; + +static const u32 golden_settings_polaris10_a11_sdma1[] = { mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, @@ -142,14 +154,16 @@ static const u32 golden_settings_polaris10_a11[] = mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; -static const u32 cz_golden_settings_a11[] = -{ +static const u32 cz_golden_settings_a11_sdma0[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, +}; + +static const u32 cz_golden_settings_a11_sdma1[] = { mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, @@ -158,22 +172,22 @@ static const u32 cz_golden_settings_a11[] = mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, }; -static const u32 cz_mgcg_cgcg_init[] = -{ +static const u32 cz_mgcg_cgcg_init_sdma0[] = { mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, - mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; -static const u32 stoney_golden_settings_a11[] = -{ +static const u32 cz_mgcg_cgcg_init_sdma1[] = { + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100, +}; + +static const u32 stoney_golden_settings_a11_sdma0[] = { mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, }; -static const u32 stoney_mgcg_cgcg_init[] = -{ +static const u32 stoney_mgcg_cgcg_init_sdma0[] = { mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, }; @@ -194,52 +208,110 @@ static const u32 stoney_mgcg_cgcg_init[] = * buffers. */ -static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) +static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev, const u32 instance_id) { + ASSERT(instance_id < adev->sdma.num_instances); + switch (adev->asic_type) { case CHIP_FIJI: - amdgpu_device_program_register_sequence(adev, - fiji_mgcg_cgcg_init, - ARRAY_SIZE(fiji_mgcg_cgcg_init)); - amdgpu_device_program_register_sequence(adev, - golden_settings_fiji_a10, - ARRAY_SIZE(golden_settings_fiji_a10)); + if (instance_id == 0) { + amdgpu_device_program_register_sequence( + adev, + fiji_mgcg_cgcg_init_sdma0, + ARRAY_SIZE(fiji_mgcg_cgcg_init_sdma0)); + amdgpu_device_program_register_sequence( + adev, + golden_settings_fiji_a10_sdma0, + ARRAY_SIZE(golden_settings_fiji_a10_sdma0)); + } else { + amdgpu_device_program_register_sequence( + adev, + fiji_mgcg_cgcg_init_sdma1, + ARRAY_SIZE(fiji_mgcg_cgcg_init_sdma1)); + amdgpu_device_program_register_sequence( + adev, + golden_settings_fiji_a10_sdma1, + ARRAY_SIZE(golden_settings_fiji_a10_sdma1)); + } break; case CHIP_TONGA: - amdgpu_device_program_register_sequence(adev, - tonga_mgcg_cgcg_init, - ARRAY_SIZE(tonga_mgcg_cgcg_init)); - amdgpu_device_program_register_sequence(adev, - golden_settings_tonga_a11, - ARRAY_SIZE(golden_settings_tonga_a11)); + if (instance_id == 0) { + amdgpu_device_program_register_sequence( + adev, + tonga_mgcg_cgcg_init_sdma0, + ARRAY_SIZE(tonga_mgcg_cgcg_init_sdma0)); + amdgpu_device_program_register_sequence( + adev, + golden_settings_tonga_a11_sdma0, + ARRAY_SIZE(golden_settings_tonga_a11_sdma0)); + } else { + amdgpu_device_program_register_sequence( + adev, + tonga_mgcg_cgcg_init_sdma1, + ARRAY_SIZE(tonga_mgcg_cgcg_init_sdma1)); + amdgpu_device_program_register_sequence( + adev, + golden_settings_tonga_a11_sdma1, + ARRAY_SIZE(golden_settings_tonga_a11_sdma1)); + } break; case CHIP_POLARIS11: case CHIP_POLARIS12: case CHIP_VEGAM: - amdgpu_device_program_register_sequence(adev, - golden_settings_polaris11_a11, - ARRAY_SIZE(golden_settings_polaris11_a11)); + if (instance_id == 0) { + amdgpu_device_program_register_sequence( + adev, + golden_settings_polaris11_a11_sdma0, + ARRAY_SIZE(golden_settings_polaris11_a11_sdma0)); + } else { + amdgpu_device_program_register_sequence( + adev, + golden_settings_polaris11_a11_sdma1, + ARRAY_SIZE(golden_settings_polaris11_a11_sdma1)); + } break; case CHIP_POLARIS10: - amdgpu_device_program_register_sequence(adev, - golden_settings_polaris10_a11, - ARRAY_SIZE(golden_settings_polaris10_a11)); + if (instance_id == 0) { + amdgpu_device_program_register_sequence( + adev, + golden_settings_polaris10_a11_sdma0, + ARRAY_SIZE(golden_settings_polaris10_a11_sdma0)); + } else { + amdgpu_device_program_register_sequence( + adev, + golden_settings_polaris10_a11_sdma1, + ARRAY_SIZE(golden_settings_polaris10_a11_sdma1)); + } break; case CHIP_CARRIZO: - amdgpu_device_program_register_sequence(adev, - cz_mgcg_cgcg_init, - ARRAY_SIZE(cz_mgcg_cgcg_init)); - amdgpu_device_program_register_sequence(adev, - cz_golden_settings_a11, - ARRAY_SIZE(cz_golden_settings_a11)); + if (instance_id == 0) { + amdgpu_device_program_register_sequence( + adev, + cz_mgcg_cgcg_init_sdma0, + ARRAY_SIZE(cz_mgcg_cgcg_init_sdma0)); + amdgpu_device_program_register_sequence( + adev, + cz_golden_settings_a11_sdma0, + ARRAY_SIZE(cz_golden_settings_a11_sdma0)); + } else { + amdgpu_device_program_register_sequence( + adev, + cz_mgcg_cgcg_init_sdma1, + ARRAY_SIZE(cz_mgcg_cgcg_init_sdma1)); + amdgpu_device_program_register_sequence( + adev, + cz_golden_settings_a11_sdma1, + ARRAY_SIZE(cz_golden_settings_a11_sdma1)); + } break; case CHIP_STONEY: + amdgpu_device_program_register_sequence( + adev, + stoney_mgcg_cgcg_init_sdma0, + ARRAY_SIZE(stoney_mgcg_cgcg_init_sdma0)); amdgpu_device_program_register_sequence(adev, - stoney_mgcg_cgcg_init, - ARRAY_SIZE(stoney_mgcg_cgcg_init)); - amdgpu_device_program_register_sequence(adev, - stoney_golden_settings_a11, - ARRAY_SIZE(stoney_golden_settings_a11)); + stoney_golden_settings_a11_sdma0, + ARRAY_SIZE(stoney_golden_settings_a11_sdma0)); break; default: break; @@ -745,6 +817,8 @@ static int sdma_v3_0_start(struct amdgpu_device *adev, const u32 instance_id) { int r; + sdma_v3_0_init_golden_registers(adev, instance_id); + /* disable sdma engine before programing it */ sdma_v3_0_ctx_switch_enable(adev, instance_id, false); sdma_v3_0_enable(adev, instance_id, false); @@ -1162,8 +1236,6 @@ static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int i, r; - sdma_v3_0_init_golden_registers(adev); - for (i = 0; i < adev->sdma.num_instances; ++i) { r = sdma_v3_0_start(adev, i); if (r) -- 2.55.0
