Refactor golden registers initialization to take the SDMA engine instance ID as an argument and only program the golden registers for one SDMA engine at once.
Signed-off-by: Timur Kristóf <[email protected]> --- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 43 +++++++++++++++++++------- 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 0743b782527a..a771e9ab3a9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -61,16 +61,22 @@ static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { SDMA1_REGISTER_OFFSET }; -static const u32 golden_settings_iceland_a11[] = { +static const u32 golden_settings_iceland_a11_sdma0[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, +}; + +static const u32 golden_settings_iceland_a11_sdma1[] = { mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, }; -static const u32 iceland_mgcg_cgcg_init[] = { +static const u32 iceland_mgcg_cgcg_init_sdma0[] = { mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, - mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 +}; + +static const u32 iceland_mgcg_cgcg_init_sdma1[] = { + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100, }; /* @@ -90,16 +96,29 @@ static const u32 iceland_mgcg_cgcg_init[] = { * buffers. */ -static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) +static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev, const u32 instance_id) { switch (adev->asic_type) { case CHIP_TOPAZ: - amdgpu_device_program_register_sequence(adev, - iceland_mgcg_cgcg_init, - ARRAY_SIZE(iceland_mgcg_cgcg_init)); - amdgpu_device_program_register_sequence(adev, - golden_settings_iceland_a11, - ARRAY_SIZE(golden_settings_iceland_a11)); + if (instance_id == 0) { + amdgpu_device_program_register_sequence( + adev, + iceland_mgcg_cgcg_init_sdma0, + ARRAY_SIZE(iceland_mgcg_cgcg_init_sdma0)); + amdgpu_device_program_register_sequence( + adev, + golden_settings_iceland_a11_sdma0, + ARRAY_SIZE(golden_settings_iceland_a11_sdma0)); + } else { + amdgpu_device_program_register_sequence( + adev, + iceland_mgcg_cgcg_init_sdma1, + ARRAY_SIZE(iceland_mgcg_cgcg_init_sdma1)); + amdgpu_device_program_register_sequence( + adev, + golden_settings_iceland_a11_sdma1, + ARRAY_SIZE(golden_settings_iceland_a11_sdma1)); + } break; default: break; @@ -469,6 +488,8 @@ static int sdma_v2_4_start(struct amdgpu_device *adev, const u32 instance_id) { int r; + sdma_v2_4_init_golden_registers(adev, instance_id); + /* halt the engine before programing */ sdma_v2_4_enable(adev, instance_id, false); @@ -871,8 +892,6 @@ static int sdma_v2_4_hw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int i, r; - sdma_v2_4_init_golden_registers(adev); - for (i = 0; i < adev->sdma.num_instances; ++i) { r = sdma_v2_4_start(adev, i); if (r) -- 2.55.0
