From: Taimur Hassan <[email protected]> This version brings along the following updates: - Fix HDMI FRL FFE compliance test and adjust FRL LT timeout. - Align eDP DSC link policy to minimize lane count. - Add AS-SDP V3 support for VESA Panel Replay. - Add DPG force-on-flip support. - Log PSR/Replay status and exit PSR/Replay on non-modeset full updates. - Reject invalid per-mode FreeSync timing and set VRR_EN state. - Align VRR timing gate with FreeSync module. - Warn on unadvertised modes without scaling. - Use DMUB to notify PME and update DMU cmd header. - Do not allow vbios version of dmubfw in the driver. - Use picoseconds for line time and correct next frame calculation. - Fix YUV422 semi-planar color blurring and UPSP chroma upsampling. - Reset UPSP and pre-CSC registers on DCN6 DPP reset. - Handle exit LS in second ISHARP programming block. - Remove hard-coded min dcfclk for AC. - Do not WARN when removing an unallocated MST payload. - Various cleanups, KUnit test fixes and debug flag gating.
Acked-by: Tom Chung <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Ray Wu <[email protected]> --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5bd990138f20..f4fefa7c9ab8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -68,7 +68,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.402" +#define DC_VER "3.2.403" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC -- 2.43.0
