From: Samson Tam <[email protected]> [Why] The hardware programming guide indicates that we must exit LS before any coefficient writes. ISHARP LUT table write occurs earlier to handle case where only sharpness level has changed. So it occurs before exit LS
[How] Add dpp401_power_on_isharp call to explicitly handle exit LS for ISHARP programming Call power_on_isharp on before and power_on_isharp off after ISHARP programming in both cases Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Samson Tam <[email protected]> Signed-off-by: Ray Wu <[email protected]> --- .../amd/display/dc/dpp/dcn401/dcn401_dpp.h | 8 ++-- .../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 40 +++++++++++++------ .../amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c | 7 ++++ 3 files changed, 38 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h index f1530e8805cb..e49be524b31c 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h @@ -757,10 +757,6 @@ enum dcn401_dscl_mode_sel dpp401_dscl_get_dscl_mode( const struct scaler_data *data, bool dbg_always_scale); -void dpp401_power_on_dscl( - struct dpp *dpp_base, - bool power_on); - void dpp401_dscl_set_recout( struct dcn401_dpp *dpp, const struct rect *recout); @@ -793,4 +789,8 @@ void dpp401_dscl_program_easf( struct dpp *dpp_base, const struct scaler_data *scl_data); +void dpp401_power_on_isharp( + struct dpp *dpp_base, + bool power_on); + #endif /* __DCN401_DPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 6e85890e44f7..adb3f155d051 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -146,7 +146,7 @@ enum dcn401_dscl_mode_sel dpp401_dscl_get_dscl_mode( return DCN401_DSCL_MODE_SCALING_420_YCBCR_ENABLE; } -void dpp401_power_on_dscl( +static void dpp401_power_on_dscl( struct dpp *dpp_base, bool power_on) { @@ -173,6 +173,25 @@ void dpp401_power_on_dscl( } } +void dpp401_power_on_isharp( + struct dpp *dpp_base, + bool power_on) +{ + struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); + + if (power_on) { + /* exit LS prior to programming ISHARP LUT */ + REG_UPDATE_2(ISHARP_DELTA_LUT_MEM_PWR_CTRL, + ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, + ISHARP_DELTA_LUT_MEM_PWR_DIS, 1); + REG_WAIT(ISHARP_DELTA_LUT_MEM_PWR_CTRL, + ISHARP_DELTA_LUT_MEM_PWR_STATE, 0, 1, 100); + } else { + REG_UPDATE_SEQ_2(ISHARP_DELTA_LUT_MEM_PWR_CTRL, + ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, + ISHARP_DELTA_LUT_MEM_PWR_DIS, 0); + } +} static void dpp401_dscl_set_lb( struct dcn401_dpp *dpp, @@ -964,13 +983,6 @@ void dpp401_dscl_program_isharp(struct dpp *dpp_base, *bs_coeffs_updated = false; PERF_TRACE(); - /*power on isharp_delta_mem first*/ - REG_UPDATE_2(ISHARP_DELTA_LUT_MEM_PWR_CTRL, - ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, - ISHARP_DELTA_LUT_MEM_PWR_DIS, 1); - - REG_WAIT(ISHARP_DELTA_LUT_MEM_PWR_CTRL, - ISHARP_DELTA_LUT_MEM_PWR_STATE, 0, 1, 100); /* ISHARP_MODE */ REG_SET_6(ISHARP_MODE, 0, @@ -1049,11 +1061,6 @@ void dpp401_dscl_program_isharp(struct dpp *dpp_base, } } - /*power on isharp_delta_mem first*/ - REG_UPDATE_SEQ_2(ISHARP_DELTA_LUT_MEM_PWR_CTRL, - ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, - ISHARP_DELTA_LUT_MEM_PWR_DIS, 0); - PERF_TRACE(); } // dpp401_dscl_program_isharp /** @@ -1096,7 +1103,10 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, (dpp->scl_data.dscl_prog_data.sharpness_level != scl_data->dscl_prog_data.sharpness_level)) { /* ISHARP_DELTA_LUT */ + dpp401_power_on_isharp(dpp_base, true); dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); + dpp401_power_on_isharp(dpp_base, false); + dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level; memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta, sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE); @@ -1159,7 +1169,9 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, if (dscl_mode == DCN401_DSCL_MODE_SCALING_444_BYPASS) { if (dpp->base.ctx->dc->config.prefer_easf) dpp401_dscl_disable_easf(dpp_base, scl_data); + dpp401_power_on_isharp(dpp_base, true); dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &bs_coeffs_updated); + dpp401_power_on_isharp(dpp_base, false); return; } @@ -1193,7 +1205,9 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, * WB scaler coeffs and toggle coeff RAM together */ //if (dpp->base.ctx->dc->config.prefer_easf) + dpp401_power_on_isharp(dpp_base, true); dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &bs_coeffs_updated); + dpp401_power_on_isharp(dpp_base, false); dpp401_dscl_set_scl_filter(dpp, scl_data, ycbcr, bs_coeffs_updated); /* Edge adaptive scaler function configuration */ diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c index f030b2a0a1f4..d1a81e5616b3 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c @@ -166,7 +166,10 @@ void dpp60_dscl_set_scaler_manual_scale(struct dpp *dpp_base, (dpp->scl_data.dscl_prog_data.sharpness_level != scl_data->dscl_prog_data.sharpness_level)) { /* ISHARP_DELTA_LUT */ + dpp401_power_on_isharp(dpp_base, true); dpp401_dscl_set_isharp_filter(dpp401, scl_data->dscl_prog_data.isharp_delta); + dpp401_power_on_isharp(dpp_base, false); + dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level; memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta, sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE); @@ -230,7 +233,9 @@ void dpp60_dscl_set_scaler_manual_scale(struct dpp *dpp_base, if (dscl_mode == DCN401_DSCL_MODE_SCALING_444_BYPASS) { if (dpp->base.ctx->dc->config.prefer_easf) dpp401_dscl_disable_easf(dpp_base, scl_data); + dpp401_power_on_isharp(dpp_base, true); dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &bs_coeffs_updated); + dpp401_power_on_isharp(dpp_base, false); return; } @@ -261,7 +266,9 @@ void dpp60_dscl_set_scaler_manual_scale(struct dpp *dpp_base, * WB scaler coeffs and toggle coeff RAM together */ //if (dpp->base.ctx->dc->config.prefer_easf) + dpp401_power_on_isharp(dpp_base, true); dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &bs_coeffs_updated); + dpp401_power_on_isharp(dpp_base, false); dpp401_dscl_set_scl_filter(dpp401, scl_data, ycbcr, bs_coeffs_updated); /* Edge adaptive scaler function configuration */ -- 2.43.0
