On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote: > [GK] If you don't use ARM, you still get hardened SDRAM controller and > GBE MACs.
Yes, that's what I was saying: you cannot get rid of them (i.e. use their pins like other IOs). So you need to use the Zynq-specific features of Vivado, interface your design to the hardened AXI system, use some obscure Vivado "wizard" to set up the SDRAM, and write a software driver for Xilinx's GbE MAC. All doable, but annoying. [GK] Well, you don't have to write it. It is already available for RTOS and linux. But it's true - it occupies MIO bank and dedicated DDR port. But this is axi and can be easily accessible from PL part. How many IOs do you need? > > * we want to avoid RTMs and instead put the DAC/ADCs on the AMC card > > and have analog plug-ins using the FMC form factor (see my document). > > **Are you sure you would get noise performance from such setup that > > satisfies you? > > Unless the FMC connector is particularly bad with analog signals, I > think it should not be worse than the current hardware. [GK] All > depends how you deliver the clock for such DAC. This is the weakest point of such solution. The DACs will be mounted on the DSP cards (AMC directly), not the RF daughtercards. And the DSP cards will have an external clocking option, that may use semi-rigid coax if need be. [GK] OK, if you make clock splitter and deliver the clocks for both DACs and RF modules externally, this should work. Another issue are ground loops, so clock and RF SMA outputs may need to be isolated. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
