When venturing into multi-tasking code, learning just how non-atomic OI and NI are (were) is (was) a hard lesson. Now it's going to be so easy ;-).
I guess in a few decades when all pre-z13 machines are retired I can simplify a bunch of code. sas On Mon, Jul 31, 2017 at 10:16 AM, Gary Weinhold <[email protected]> wrote: > I think (TS) Test and Set was/is atomic and AFAIK was the earliest > implemented atomic instruction. I think it addressed the requirement to > allow interruptible code to fetch, test, and modify a single byte on a > single CPU machine with integrity. An external or I/O interrupt could > undermine the integrity of a TM, Bx, OI/NI instruction sequence in that > environment. > > Gary Weinhold > Senior Application Architect > > DATAKINETICS | Data Performance & Optimization > > Phone: +1.613.523.5500 x216<tel:+1.613.523.5500%20x216> > Email: [email protected]<mailto:[email protected]> > > [http://www.dkl.com/wp-content/uploads/2015/07/dkl_logo.png]< > http://www.dkl.com/> > > Visit us online at www.DKL.com<http://www.dkl.com/> > > [http://www.dkl.com/wp-content/uploads/2015/08/banner.png]<h > ttp://www.dkl.com/mailsig> > > E-mail Notification: The information contained in this email and any > attachments is confidential and may be subject to copyright or other > intellectual property protection. If you are not the intended recipient, > you are not authorized to use or disclose this information, and we request > that you notify us by reply mail or telephone and delete the original > message from your mail system. > > > > __________ > On 2017-07-30 23:58, Jon Perryman wrote: > > > I believe the only true atomic instructions are CS and CSD. PLO is > considered atomic when using the same lock. Concurrency is only guaranteed > with some sort of lock which is to expensive to implement for every > instruction and for storage being referenced / modified. The odds of a > single instruction concurrency issue is extremely low (essentially 0) but > still possible. CPU's, storage, and pipelines are exactly the same. Using > MVC example, the speed of movement would be exactly the same therefore you > should never experience a problem. If on the other hand, there was > something to make one MVC operate at a different speed (e.g. pipeline > algorithm), then you would have a concurrency issue. > Regards, Jon. > On Sunday, July 30, 2017 5:50 PM, Phil Smith <[email protected]><mailto: > [email protected]> wrote: > > Mmm...I'm pretty sure a single instruction is still atomic. I'm sure Peter > Relson or one of the other IBMers will chime in, but it there has to be > some sort of interlock at some level. And I've debugged plenty of > concurrency problems, never seen a mixture from a single instruction! > > ...phsiii > -- sas
