On Mon, 31 Jul 2017 22:45:51 -0400, Charles Mills ([email protected]) wrote about "Re: Question about CPUs" (in <[email protected]>):
> People are confusing single processors with multiple processors. > > On a single processor, almost all instructions are atomic. The > exceptions are the obvious ones like MVCL, which are obviously > designed to take an interrupt and resume. Yes, all interruptions > are at an instruction boundary, and the IAR is saved and resumed. The term you are groping for here is "memory interlock". This was coined by IBM in regard to the TS instruction in that it imposes a lock on its target byte to prevent any other processor in the SMP configuration from manipulating that byte until its operation is complete. In a uniprocessor system, the memory interlock is redundant. In a multiprocessor system it saves your arse. So, instructions like TS, CS, CSD, etc. are *memory atomic* across SMP configurations, not just non-interruptible. -- Regards, Dave [RLU #314465] *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* [email protected] (David W Noon) *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
