The term you are groping for here is "memory interlock". This was coined > by IBM in regard to the TS instruction in that it imposes a lock on its > target byte to prevent any other processor in the SMP configuration from > manipulating that byte until its operation is complete. >
I believe the thread has been ignoring the earlier reference to "block concurrent" that the Principles of Operation uses to explain the issue. To redefine the concept of interrupts does not make it more clear in my opinion. Mind you, on a single CPU system we still have channels that access memory, though some of that access is self-inflicted and predictable. Oh, and while it does not apply to CP's, you can have your IFL in SMT mode... I grunted a lot at the early gcc port that was using CSD to store a double word, inspired by architectures where such operations were not atomic. There's more "common knowledge" from the other side that does not apply to IBM Z.
