People are confusing single processors with multiple processors. On a single processor, almost all instructions are atomic. The exceptions are the obvious ones like MVCL, which are obviously designed to take an interrupt and resume. Yes, all interruptions are at an instruction boundary, and the IAR is saved and resumed.
On a multi-processor, everything changes. Processor one's MVC might be "interrupted" (in the generic sense of the word) by processor two. Processor two's NI might be interrupted by processor one. The only things that are atomic are those so designated in the PoOp. There is no need to suspend one instruction and resume it because each processor has its own PSW, IAR and GP registers. The processors never stop. The other processor just runs along in parallel. You work on lots of projects. Your boss is always coming in and yelling "wait! Stop working on that! Work on this instead!" (Sound familiar?) But you're a very organized person and you always get to a good stopping point and make notes of where you are before you stop work on a project, so you can pick up again where you left off. You're a single, multi-tasking CPU. Now suppose there are two of you sharing an office. You're a two-processor box! You each have your own pencils and notepads, and the other guy is just as organized as you are, so no problem, right? The only problem is that you share the same whiteboard. Most of the time you write in different areas of the whiteboard, so it works out just fine. But unless you are very, very careful you COULD both end up writing on the same spot of the whiteboard at the same time ... and writing garbage, even though what each of you writes is organized, logical and correct. Charles -----Original Message----- From: IBM Mainframe Assembler List [mailto:[email protected]] On Behalf Of Robin Vowels Sent: Monday, July 31, 2017 8:42 PM To: [email protected] Subject: Re: Question about CPUs From: "Gary Weinhold" <[email protected]> Sent: Tuesday, August 01, 2017 12:16 AM > I think (TS) Test and Set was/is atomic and AFAIK was the earliest > implemented atomic instruction. I think that the entire /360 user instruction set would have been of that kind. AFIK there was no provision to suspend any instrction and to resume it after an interrupt. The instruction had to be allowed to complete, and the IAR saved, so that when control was passed back to the interrupted program, the next instruction was executed.
