On 2019-01-10, at 09:46:38, Peter Relson wrote: 
> 
> Many of us grew up with machines where OI and some other instructions were 
> done in multiple stages, and at just the wrong point could result in lost 
> data if CS/CDS was being used. You could not mix and match. 
>  
Ever since I learned of the NIL and OIL macros, I have wondered why MVI
and STC did not have the same exposure as OI and NI:

The storage bus has been at least 16 bits wide as long as anyone can
remenber.  So two processers both fetch the same 16-bit frame.  One
updates the even half; the other into the odd half.  Both store.
Last guy wins (sort of).

Are NI and OI older than CS?  Was there then a precursor of NIL using
test-and-set?

PDP-6 had a peculiar read-pause-write memory cycle, bypassing the restore
phase of core memory access.  This was a performance benefit and serialized
memory updating instructions.

-- gil

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