> But in practice there existed no machines with more than one CPU What was the IBM 9020, chopped liver? Bendix G-21? Burroughs B5000? Burroughs D825? BULL Gamma 60? CDC 6600? GE 635?Arguably, the Honeywell H-800? UNIVAC 1108?
-- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 ________________________________________ From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> on behalf of Tony Harminc <t...@harminc.com> Sent: Thursday, January 10, 2019 5:08 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Multi CPU interlock question On Thu, 10 Jan 2019 at 13:44, Paul Gilmartin <00000014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > Ever since I learned of the NIL and OIL macros, I have wondered why MVI > and STC did not have the same exposure as OI and NI: > > The storage bus has been at least 16 bits wide as long as anyone can remenber. I remember the 360/30 (used one in high school), and I'm pretty sure it had an 8-bit bus. But I could be wrong. > So two processers both fetch the same 16-bit frame. One > updates the even half; the other into the odd half. Both store. > Last guy wins (sort of). Yup. But in practice there existed no machines with more than one CPU until the 360/65MP, and I don't think there ever existed a 360 or 370 with more than one processor that had anything smaller than a 64-bit bus. More to the point, I'm not sure there was a strong definition of storage access by multiple processors until fairly late in the S/370 POO days. > Are NI and OI older than CS? NI and OI are original with S/360. CS and CDS came only with DAT in S/370. Lynn Wheeler has written extensively here on CS and its origins and the internal battles associated with it. >Was there then a precursor of NIL using test-and-set? I don't believe so. (That would be OIL, wouldn't it? TS turns bits ON.) Tony H.
