On Thu, 10 Jan 2019 at 17:54, gah <[email protected]> wrote: > > I remember the 360/30 (used one in high school), and I'm pretty sure > > it had an 8-bit bus. But I could be wrong. > > The 360/30 has an 8 bit bus and 8 bit ALU.
Thanks for confirming my, uh memory. > > So two processers both fetch the same 16-bit frame. One > > updates the even half; the other into the odd half. Both store. > > Last guy wins (sort of). > > With only one processor, you still have I/O to consider. But I/O is generally not covered by the same strong block concurrency rules that apply to other CPUs. Weaker rules apply in most cases. > And for the 360 and 370, the interval timer. Tradition was to read > the old value and replace it with.a new value with one MVC. More than tradition - documented in the S/360 POO as the only certain way of not missing a timer update. But that scheme was not to protect against concurrent storage access by another processor (whether CPU or channel) *during instruction execution*, but to avoid a timer update from occuring *between* instructions, as could happen if, say, Load/Store were used instead of MVC. Tony H.
