On 2019-01-10, at 15:53:59, gah wrote: > >> So two processers both fetch the same 16-bit frame. One >> updates the even half; the other into the odd half. Both store. >> Last guy wins (sort of). > > With only one processor, you still have I/O to consider. > I understand that on some systems the channels stole microcycles from the CPU, so if CPU instructions were not micro-interruptable the serialization was provided.
Bit-spinning for I/O was frequently used, but risky for the naive. > And for the 360 and 370, the interval timer. Tradition was to read > the old value and replace it with.a new value with one MVC. > i've heard of that. It required dedicating some storage loctions adjacent to the interval timer. Was the interval timer always updated by an interrupt handler? But I'm still puzzled as to why on some systems with a 16-bit bus NIL and OIL were required for serialization but MVI and STC had no such hazard. -- gil
