So it was written, and it is so done. sas On Tue, Oct 20, 2020 at 6:35 PM Charles Mills <charl...@mcn.org> wrote:
> Unless I am thinking fuzzily, an interrupted MVCL leaves the PSW pointing > to > the MVCL (not past it) and the relevant registers incremented and > decremented appropriately, so the supervisor may dispatch other tasks on > the > affected CPU, let them run as they will, and then resume the interrupted > task when appropriate. The task will take off with the MVCL continuing from > where it left off. > >
