I'm pretty sure that testing for pending interrupts didn't slow down CLCL or MVCL on the 370/165 or 370/168. But the microinstruction was 108 bits; longer if you had an emulator feature.
-- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 ________________________________________ From: IBM Mainframe Assembler List [[email protected]] on behalf of Steve Smith [[email protected]] Sent: Tuesday, October 20, 2020 6:36 PM To: [email protected] Subject: Re: Conditional MVCL macro? Interrupts can only be handled between instructions (don't ask me how pipelining figures).... except, MVCL has the potential to delay that too long, so it (and a handful of others) were made to be interruptible. Probably, that just means the micro/milli-code program gets interrupted between micro/milli-code instructions. Possibly, that affects its performance negatively. Anyway, for MVCLE, the 4K limit means it can't run very long anyway, so yeah, it does help keep interrupts flowing. sas On Tue, Oct 20, 2020 at 6:16 PM Keven <[email protected]> wrote: > > > > > I’d say you were both correct. > Keven > > > > > > > > > > > On Tue, Oct 20, 2020 at 5:01 PM -0500, "Paul Gilmartin" < > [email protected]> wrote: > > > > > > > > > > > On 2020-10-20, at 14:58:52, Steve Smith wrote: > > > > There's actually a big difference between MVCL being interruptible, and > > MVCLE stopping periodically before it's finished. The latter is not > > interruptible, it just stops before completion periodically for the > program > > to do something else if it wants to. ... > > > I thought it was so that supervisor could dispatch another task. > > -- gil >
