"IBM Mainframe Assembler List" <ASSEMBLER-LIST@LISTSERV.UGA.EDU> wrote on
01/20/2022 06:30:02 AM:
> Regardless of the instruction used to load the source register, CVD
treats
> it as a signed F-word. So any value with bit 32 (high-order bit of
lower
> half) on will be converted to a negative PD number. So,
That is true. But I am using CVDG in my generic subroutine.
Sincerely,
Dave Clark
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