"IBM Mainframe Assembler List" <[email protected]> wrote on
02/03/2022 06:49:33 PM:
> Here is another possibility that uses instructions which have been
> available since the publication of the original z/Architecture
> Principles of Operation in December 2000. It is only one
> instruction longer (and four instruction bytes longer) than the
> scheme offered by Dan Greiner, although not as nifty!
OK, let's examine this. I follow what lines 1 to 3 will do. But
it doesn't seem that line 4 will do what I need. The reason I am confused
is because the PoPs manual says that line 3, in this case, will not change
the content of R0, thus bits 28-31 are the same as they were after line 2.
In that case, how does line 4 get R0 bits 28-29 into bit positions 30-31
where they need to be for line 5 to work correctly?
1. LLGC R0,BYTE GET ENCODED BYTE (NEED BITS 24-27)
2. SRL R0,4(0) SHIFT OUT RIGHTMOST 4 BITS
3. SRLG R1,R0,2(0) SHIFT NEXT 2 BITS INTO R1 (R0 UNCHANGED)
4. NILL R0,B'11' (CONFUSED, WHAT DOES THIS ACTUALLY DO?)
5. AHI R0,C'1' ORIG. BITS 24-25 TO ZONED DECIMAL
6. AHI R1,C'1' ORIG. BITS 26-27 TO ZONED DECIMAL
Sincerely,
Dave Clark
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