The instruction SRLG R1,R0,2(0) loads R1 with a shifted copy or R0. It's not a double shift.
-- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 ________________________________________ From: IBM Mainframe Assembler List [[email protected]] on behalf of Dave Clark [[email protected]] Sent: Friday, February 4, 2022 12:26 PM To: [email protected] Subject: Re: Making Encoded Bits Human Readable "IBM Mainframe Assembler List" <[email protected]> wrote on 02/04/2022 12:11:53 PM: > Instruction 3 doesn't affect R0, so it still has the 4 leftmost bits > from instruction 2. Instruction 4 removes the left two bits, leaving > only the right two bits. In that case, those are the wrong two bits that would be needed. The right two bits were shifted into R1 so it is the left two bits that are needed. Correct? Sincerely, Dave Clark -- int.ext: 91078 direct: (937) 531-6378 home: (937) 751-3300 Winsupply Group Services 3110 Kettering Boulevard Dayton, Ohio 45439 USA (937) 294-5331 ********************************************************************************************* This email message and any attachments is for use only by the named addressee(s) and may contain confidential, privileged and/or proprietary information. If you have received this message in error, please immediately notify the sender and delete and destroy the message and all copies. All unauthorized direct or indirect use or disclosure of this message is strictly prohibited. No right to confidentiality or privilege is waived or lost by any error in transmission. *********************************************************************************************
