Seems to me I ran into this issue trying to set up the parms for PLO. The comparison and replacement values are 128 bits IIRC.
Charles -----Original Message----- From: IBM Mainframe Assembler List [mailto:[email protected]] On Behalf Of Don Higgins Sent: Monday, April 18, 2022 9:03 AM To: [email protected] Subject: Re: Quadword constant >What instructions take fixed quadword operas? I imagine some variant of Divide. Yes, DLG and DLGR operate on 128 bit dividend in 64 bit r1 and r1+1. But since the dividend is in registers, there is no requirement for quad word alignment.
