On Apr 18, 2022, at 10:03:05, Don Higgins wrote: > >> What instructions take fixed quadword operas? I imagine some variant of >> Divide. > > Yes, DLG and DLGR operate on 128 bit dividend in 64 bit r1 and r1+1. But > since the dividend is in registers, there is no requirement for quad word > alignment. > But there is no HLLASM construct to generate that 128-bit dividend, Whether aligned for not. Imagine: TERA. EQU 1000000*1000000 DIVIDEND DC AL8(TERA)
Why not? DIVIDEND DC x'000000E8D4A51000' Hardly suffices. > -----Original Message----- > From: Paul Gilmartin > Sent: Monday, April 18, 2022 11:40 AM > > But it becomes increasingly absurd that a 64-bit machine is supported by > only a 32-bit assembler. -- gil
