"IBM Mainframe Assembler List" <[email protected]> wrote on
11/21/2023 04:49:37 PM:
> On 11/21/23 14:32:27, Tom Marchant wrote:
> > Modern processors use a 256-byte cache line, with separate caches for
> > instructions and data. A cache line maps to 256 bytes of storage on a
> > 256-byte boundary. There are performance penalties when the same line
> > of storage needs to be in both the instruction cache and the data
cache.
> Is it recommended, then, to cache-line align LTORG so instructions
> and data don't share a cache line. Is there an instruction that
> will continue to do this for future hardware?
So, how does one force a 256-byte alignment? I have LOCTR now
placing all of my static data areas at the beginning of the program (after
the initial jump to the start of the code area). How do I pad that data
area so that the following code area starts on the next 256-byte boundary?
Sincerely,
Dave Clark
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