Hi Sean, Out of interest, have you measured what happens if you don't send the spdif though the buffer chip - i.e. disconnect or hardwire to dc in the Xilinx [probably such that the spdif output is low and hence not sourcing current for the output potential divider]. This should minimise the switching currents in the buffer.
For reference one of the after market clock guys claims 3ps rms jitter (3sigma rather than 1sigma) [taken from www.tentlabs.com]. So perhaps there is potential to futher improve with expensive after market clocks, but we are already getting low jitter in comparison to lots of digital gear. Adrian -- Triode _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
