Sean Wrote: 
> Also its clock is PLL driven so it is unlikely that optimizing the
> external clock source would have a huge impact - I would expect the
> PLL's jitter to dominate. Just guessing though - I haven't actually
> done any of these tests on SB1

In my subjective experience there is a huge benefit in replacing SB1's
external clock with a low jitter one. Subtle it is not IMHO.


-- 
NealG
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