// SRAMs are used extensively.

> If by "extensively" you mean "in certain specialized 
> applications, or where tiny amounts of RAM are needed", then 
> yes, I'd agree.

Odd that, you didn't do that one post ago.

// .. buffer chip is a 128K x 8 (1Mbit) SRAM.

> Do you realize that you are having this argument with the 
> person who designed the hardware in question? SLIMP3 (2001) 

And failed to thoroughly document the design change? All I am telling
you is I had reason to say what I wrote given the information you still
have up on your website. So sue me. It's great the SB has no SRAM. It
still doesn't mean it'll never spit out a single erroneous bit in its
processing chain, ever, statistically irrelevant as that may be.

I love the SB. I happen to think you made yourself look poorly replying
the way you did in this thread, your engineering merits aside.

Thanks.

> I thought SRAMs were used in your field? Or are you talking 
> about SRAMS with ECC? 

ECC became a requirement because of the extensive use of SRAM, and
because memory corruption became an issue that was perceived as a ket
reliability aspect by major network operators. There were and have been
several conferences on this, and several NANOG sessions. Look it up.

> In any case, I suspect you are still confused as to what we're 
> even talking about here! 

You'd like to think that, but no. You claimed all memory is equally
reliable. I proved you wrong. SRAM is 1,000 times as likely to be
affected as DRAM. Whether it is or not an operational issue that
affects a particular application is a different matter altogether.

// What I was asking is data on errors during transmission from audio
CD to computer. 

> I thought you were talking about flipped memory bits...

Then you thought wrong. My question was about some evidence that indeed
the process of copying an audio CD is as error prone and unportected as
has been repeatedly stated. And I asked it nicely. I then pointed out
the occasional flipped bit is not a disaster, and that there is
circumstancial evidence to assume it may happen in computer based
reproduction chains. DRAMs are not utterly error prone, you know. It
just so happens SRAMs are "notoriously" so, and several conferences
have been dedicated to the topic.

> I didn't say that, and my goal in the first place was not to 
> offend. However in this case I would not have been doing any 
> of us a favor by just entertaining your arguments. 

You didn't make yourself a favor, first and foremost, since you made a
categoric statement that was wrong, and now can't admit to it, and
can't even utter an apology when you called someone ignorant.

I don't know everything, and never made the claim, which is why this
started with a question. You were the one claiming you had all the
answers. Or so you thought, and so you may prefer to continue to
believe, since the omnipotent SB designer is talking down to us ex
catherda as he pleases. Just like the Pope, you show human fallibility
when you talk outside your realm of authority.


-- 
pablolie
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