seanadams;183862 Wrote: > Actually I believe that was _entirely_ the matter at hand. If you refer > to the post that kicked off this silly discussion, Havoc said "I still > have to see the first flipped sram bit! This might be a problem for a > satelite out there, but not for a pc."
Let me start by agreeing with Sean and others that errors from SRAM are irrelevant to the discussion at hand. That said, I know quite a bit about this subject and I'll take advantage of this detour to provide a bit of factual information for anyone interested. First, SRAMs are 1000 times more susceptible to soft errors (SER) compared to DRAMs, as pointed out by Pablo. The reason for this is that DRAMs have a much larger capacitor in each memory cell and it takes much more induced charge to cause an error because of this. This then translates to a much lower error rate due to ionizing radiation. However, this isn't the reason one needs to use ECC for modern SRAMs. Instead, the reason has to do with problems that occur as one scales SRAM cells to smaller dimensions. Statistical dopant fluctuations lead to mismatches between the SRAM transistors and one when builds large on-chip memories arrays one can't guarantee that all the bits will be error free. So designers need to start using ECC for the larger on chip arrays. This is standard practice for designers of processors using large SRAM caches. ---Gary -- GaryB ------------------------------------------------------------------------ GaryB's Profile: http://forums.slimdevices.com/member.php?userid=3169 View this thread: http://forums.slimdevices.com/showthread.php?t=32993 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
