Because the -"close-in"- jitter is the really bad stuff. And hard to get rid of.
Look, if it wasn't all that bad: 1.) Everyone would spec their oscillator jitter down below 1 Hz. They don't, and there is a reason why. 2.) All PLLs would work wonderfully and SPDIF would sound as good as the source. (We all know that it doesn't, or at least should be open and/or aware of that possibility.) Back to that wretched TI chip..........I figured out the jitter for Fig. 13, as that is the least offensive. Had to extrapolate the 10 Hz data, but since it looks like a linear plot...... Jitter is around 75 pSec. Compare that to what they claim for > 10 kHz. Which is.....drum roll, please......around 12 pSec. -How on earth they get that number is beyond me, 'cuz I get 0.12 pSec. Must be a typo.- I hope it is a typo. Bloody awful if it isn't. Anyway, let's go with 0.12 pSec, as when you look at Fig. 12 (which is much worse and claims <1 pSec), it makes sense. So, compare 73 pSec to 0.12 pSec. Which one would you buy? The lower one, right? Wrong, because they are the same. But if your data sheet said that number... Answer your question? BTW......take that 73 pSec @ 24.5 MHz, same amount of phase noise for 11.3 MHz (256 Fs for 44.1 kHz), you get >150 pSec. Like I said, SPDIF -can- do better. Pat -- ar-t http://www.analogresearch-technology.net ------------------------------------------------------------------------ ar-t's Profile: http://forums.slimdevices.com/member.php?userid=13619 View this thread: http://forums.slimdevices.com/showthread.php?t=56425 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
