jkeny wrote: > Do they? The structure of the digital signal I2S signal (the one that > operates at chip level) is a serial stream of data bits, Right channel > sample first then followed by Left channel sample. In modern DACs there > are 32 bits in each sample. Each of these bits is clocked on a separate > tick that is derived from the clock. So it is very possible that during > the right channel sample timing will be affected by clock jitter & that > there is a completely different clock jitter profile during the left > sample processing > > You are trying to maintain that clock jitter affects both channels > identically. Again, please!! Utter hogwash. Do you know anything about > how DACs operate or is all this BS just trying to impress the lay > person? > > Do you really think that the Bit clock (which is derived from the audio > clock) times the bits into both channels synchronously?? Your lack of > the basics is really embarrassing
Oh dear. ------------------------------------------------------------------------ utgg's Profile: http://forums.slimdevices.com/member.php?userid=40900 View this thread: http://forums.slimdevices.com/showthread.php?t=103684 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/mailman/listinfo/audiophiles
