utgg wrote: 
> Oh dear.

Indeed. 

Reference: 'I2SBUS.pdf'
(https://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf)

Reality is that in i2s there is one clock line and one data line,

Changes to the shared clock line that affect one channel will affect the
other channel if the change to the clock has a duration of one data word
or more since the channels are interleaved on one data line.

This is because any change to the clock line that lasts longer than the
time to transmit one data word naturally affects the next data word for
the other channel.

So what are we talking about here?

@44 KHz  two channels are transmitted every 22 microseconds. So any
change to the clock that lasts longer than 22 microseconds will affect
both channels. any change that lasts longer than 44 microseconds will
affect both channels identically.  This corresponds to a jitter
frequency of approximately 2200 Hz.  That means that any clock jitter at
2200 Hz or lower will affect both channels identically, and any clock
jitter at 4400 Hz or lower will affect both channels somewhat.

Since we were talking about clock variations that lasted for several
seconds there is no doubt that these variations will affect both
channels identically.

So before Jkeny deflected there was another questions for him to answer:

jkeny do you OEM DACs from someone who actually understands them? That
would explain lots of things.

(BTW there is an old adage that a lawyer never asks a question that he
doesn't know the answer to. I'm not a lawyer but I've worked with
them...)


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