On Thu, 04 Jun 2026 13:06:53 +0200, Michael Tretter wrote:
> The Agilex5 SDRAM initialization contains some obscure and unclear
> workarounds, which are supposedly necessary for a successful SDRAM
> initialization.
>
> I observed a race condition between the IOSSM firmware, which is
> responsible for the SDRAM initialization, and barebox. I assume this
> race is responsible for the observed initialization failures.
>
> [...]
Applied, thanks!
[1/5] arm: socfpga: agilex5: separate EL3 init function
https://git.pengutronix.de/cgit/barebox/commit/?id=f615446b218f (link may
not be stable)
[2/5] arm: socfpga: agilex5: panic if DDR init failed
https://git.pengutronix.de/cgit/barebox/commit/?id=3791fb227199 (link may
not be stable)
[3/5] arm: socfpga: iossm: add delay to wait for firmware
https://git.pengutronix.de/cgit/barebox/commit/?id=4296d8ae1181 (link may
not be stable)
[4/5] arm: socfpga: agilex5: drop dual port hack
https://git.pengutronix.de/cgit/barebox/commit/?id=36ad90f489fb (link may
not be stable)
[5/5] arm: socfpga: agilex5: drop bank select before ddr_init
https://git.pengutronix.de/cgit/barebox/commit/?id=6685029a7c78 (link may
not be stable)
Best regards,
--
Sascha Hauer <[email protected]>
