This is a v2 of the patch series [0] to synchronize the socfpga clock driver with the kernel driver, which was applied by reverted due to a compile error.
This series split the original patch into cleanup patches to synchronize the entire socfpga clock driver with the Linux driver and another patch to apply the synchronization of the actual Agilex5 driver. Otherwise, the fix of the compile error would have resulted in inconsistent structs for the various clocks. I runtime tested this patch series only on Agilex 5, and only did build tests on the other SoCFPGA platforms. [0] https://lore.kernel.org/all/20251215-v2025-11-0-topic-socfpga-agilex5-clk-v1-1-e1270179d...@pengutronix.de/ Signed-off-by: Michael Tretter <[email protected]> --- Michael Tretter (2): clk: socfpga: sync arria10 clock initialization with kernel clk: socfpga: remove clk-phase setting Steffen Trumtrar (2): clk: socfpga: sync clock structs with kernel clk: socfpga: agilex5: sync with kernel drivers/clk/socfpga/clk-agilex5.c | 842 ++++++++++++----------------------- drivers/clk/socfpga/clk-gate-a10.c | 104 +---- drivers/clk/socfpga/clk-gate-s10.c | 32 +- drivers/clk/socfpga/clk-periph-a10.c | 39 +- drivers/clk/socfpga/clk-periph-s10.c | 66 ++- drivers/clk/socfpga/clk-pll-a10.c | 56 +-- drivers/clk/socfpga/clk-pll-s10.c | 57 ++- drivers/clk/socfpga/clk.h | 15 +- drivers/clk/socfpga/stratix10-clk.h | 48 +- 9 files changed, 498 insertions(+), 761 deletions(-) --- base-commit: 713a1e59dfea4516446822323b7c0db571cb214f change-id: 20260604-socfpga-agilex5-clk-50bede6b1c8d Best regards, -- Michael Tretter <[email protected]>
