[PATCH v2 2/4] clk: socfpga: remove clk-phase setting

[Michael Tretter]

There are no device trees that have the clk-phase property and the Linux
driver doesn't have the code. Remove the unused clk-phase setting.

Signed-off-by: Michael Tretter <m.tret...@pengutronix.de>
---
 drivers/clk/socfpga/clk-gate-a10.c | 55 --------------------------------------
 1 file changed, 55 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-a10.c 
b/drivers/clk/socfpga/clk-gate-a10.c
index e6bcc91b0490..b43e19d2ca3f 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -36,59 +36,11 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct 
clk_hw *hw,
        return parent_rate / div;
 }
 
-static int socfpga_clk_prepare(struct clk_hw *hw)
-{
-       struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hw);
-       int i;
-       u32 hs_timing;
-       u32 clk_phase[2];
-
-       if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
-               for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
-                       switch (socfpgaclk->clk_phase[i]) {
-                       case 0:
-                               clk_phase[i] = 0;
-                               break;
-                       case 45:
-                               clk_phase[i] = 1;
-                               break;
-                       case 90:
-                               clk_phase[i] = 2;
-                               break;
-                       case 135:
-                               clk_phase[i] = 3;
-                               break;
-                       case 180:
-                               clk_phase[i] = 4;
-                               break;
-                       case 225:
-                               clk_phase[i] = 5;
-                               break;
-                       case 270:
-                               clk_phase[i] = 6;
-                               break;
-                       case 315:
-                               clk_phase[i] = 7;
-                               break;
-                       default:
-                               clk_phase[i] = 0;
-                               break;
-                       }
-               }
-
-               hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
-               writel(hs_timing, ARRIA10_SYSMGR_SDMMC);
-       }
-       return 0;
-}
-
 static int clk_socfpga_enable(struct clk_hw *hw)
 {
        struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw);
        u32 val;
 
-       socfpga_clk_prepare(hw);
-
        val = readl(socfpga_clk->reg);
        val |= 1 << socfpga_clk->bit_idx;
        writel(val, socfpga_clk->reg);
@@ -115,7 +67,6 @@ static struct clk *__socfpga_gate_init(struct device_node 
*node,
 {
        u32 clk_gate[2];
        u32 div_reg[3];
-       u32 clk_phase[2];
        u32 fixed_div;
        struct clk_hw *hw_clk;
        struct socfpga_gate_clk *socfpga_clk;
@@ -153,12 +104,6 @@ static struct clk *__socfpga_gate_init(struct device_node 
*node,
                socfpga_clk->div_reg = NULL;
        }
 
-       rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
-       if (!rc) {
-               socfpga_clk->clk_phase[0] = clk_phase[0];
-               socfpga_clk->clk_phase[1] = clk_phase[1];
-       }
-
        of_property_read_string(node, "clock-output-names", &clk_name);
 
        init.name = clk_name;

-- 
2.47.3