Switch from bclk_register to clk_hw_register with clk_init_data to be more in line with the Linux driver.
Signed-off-by: Michael Tretter <[email protected]> --- drivers/clk/socfpga/clk-gate-a10.c | 27 ++++++++++++--------------- drivers/clk/socfpga/clk-periph-a10.c | 29 ++++++++++++++--------------- drivers/clk/socfpga/clk-pll-a10.c | 31 ++++++++++++++++--------------- 3 files changed, 42 insertions(+), 45 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index b66fbcdb8c54..e6bcc91b0490 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -117,10 +117,12 @@ static struct clk *__socfpga_gate_init(struct device_node *node, u32 div_reg[3]; u32 clk_phase[2]; u32 fixed_div; + struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; + const char *parent_name[SOCFPGA_MAX_PARENTS]; + struct clk_init_data init; int rc; - int i; socfpga_clk = xzalloc(sizeof(*socfpga_clk)); @@ -159,23 +161,18 @@ static struct clk *__socfpga_gate_init(struct device_node *node, of_property_read_string(node, "clock-output-names", &clk_name); - socfpga_clk->hw.clk.name = xstrdup(clk_name); - socfpga_clk->hw.clk.ops = ops; + init.name = clk_name; + init.ops = ops; + init.flags = 0; - for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) { - socfpga_clk->parent_names[i] = of_clk_get_parent_name(node, i); - if (!socfpga_clk->parent_names[i]) - break; - } + init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); + init.parent_names = parent_name; + socfpga_clk->hw.init = &init; + hw_clk = &socfpga_clk->hw; - socfpga_clk->hw.clk.num_parents = i; - socfpga_clk->hw.clk.parent_names = socfpga_clk->parent_names; - - rc = bclk_register(&socfpga_clk->hw.clk); - if (rc) { - free(socfpga_clk); + rc = clk_hw_register(NULL, hw_clk); + if (rc) return ERR_PTR(rc); - } return &socfpga_clk->hw.clk; } diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c index f9cf40b0aaf3..61b693d295f7 100644 --- a/drivers/clk/socfpga/clk-periph-a10.c +++ b/drivers/clk/socfpga/clk-periph-a10.c @@ -62,12 +62,14 @@ static struct clk *__socfpga_periph_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; + struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; + const char *parent_name[SOCFPGA_MAX_PARENTS]; + struct clk_init_data init; int rc; u32 fixed_div; u32 div_reg[3]; - int i; of_property_read_u32(node, "reg", ®); @@ -92,25 +94,22 @@ static struct clk *__socfpga_periph_init(struct device_node *node, of_property_read_string(node, "clock-output-names", &clk_name); - for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) { - periph_clk->parent_names[i] = of_clk_get_parent_name(node, i); - if (!periph_clk->parent_names[i]) - break; - } + init.name = clk_name; + init.ops = ops; + init.flags = 0; - periph_clk->hw.clk.num_parents = i; - periph_clk->hw.clk.parent_names = periph_clk->parent_names; + init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); + init.parent_names = parent_name; - periph_clk->hw.clk.name = xstrdup(clk_name); - periph_clk->hw.clk.ops = ops; + periph_clk->hw.init = &init; - rc = bclk_register(&periph_clk->hw.clk); - if (rc) { - free(periph_clk); + hw_clk = &periph_clk->hw; + + rc = clk_hw_register(NULL, hw_clk); + if (rc) return ERR_PTR(rc); - } - return &periph_clk->hw.clk; + return &hw_clk->clk; } struct clk *socfpga_a10_periph_init(struct device_node *node) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 2e58a2eb5d92..566d99563ff6 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -88,10 +88,13 @@ static struct clk *__socfpga_pll_init(struct device_node *node, const struct clk_ops *ops) { u32 reg; + struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; const char *clk_name = node->name; + const char *parent_name[SOCFGPA_MAX_PARENTS]; + struct clk_init_data init; int rc; - int i; + int i = 0; of_property_read_u32(node, "reg", ®); @@ -101,27 +104,25 @@ static struct clk *__socfpga_pll_init(struct device_node *node, of_property_read_string(node, "clock-output-names", &clk_name); - pll_clk->hw.clk.name = xstrdup(clk_name); - pll_clk->hw.clk.ops = ops; + init.name = clk_name; + init.ops = ops; + init.flags = 0; - for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) { - pll_clk->parent_names[i] = of_clk_get_parent_name(node, i); - if (!pll_clk->parent_names[i]) - break; - } + while (i < SOCFGPA_MAX_PARENTS && + (parent_name[i] = of_clk_get_parent_name(node, i)) != NULL) + i++; + init.num_parents = i; + init.parent_names = parent_name; pll_clk->bit_idx = SOCFPGA_PLL_EXT_ENA; - pll_clk->hw.clk.num_parents = i; - pll_clk->hw.clk.parent_names = pll_clk->parent_names; + hw_clk = &pll_clk->hw; clk_pll_ops.enable = clk_socfpga_enable; clk_pll_ops.disable = clk_socfpga_disable; - rc = bclk_register(&pll_clk->hw.clk); - if (rc) { - free(pll_clk); - return NULL; - } + rc = clk_hw_register(NULL, &pll_clk->hw); + if (rc) + ERR_PTR(rc); return &pll_clk->hw.clk; } -- 2.47.3
