2010/2/28 Nathan Schulte <rekl...@gmail.com>: > 2010/2/28 Gábor Stefanik <netrolller...@gmail.com>: >> OK, this dump shows the 0x280a write happening with core 3, i.e. PCIE, >> active. So, it is indeed probably the "PCIE misc configuration" >> routine. Why it's 0x280a is still a mystery to me, it should be 0x100a >> according to the specs. > Unless I'm reading the logs wrong, isn't wl setting bit 0x8000 when > core 1 is mapped (0 indexed cores, 0x18001000 mapped to space 0)? > And b43 appears to do it when core 0 is mapped (0x18000000 mapped to > space 0). b43 also reads from 0x100a after writing to 0x280a, and it > reads as 0x8000 not set (while the 0x280a check show it is set). > > This is when comparing the wl_cold and b43_cold logs. > > -Nate >
The latest patch, which is a partial success according to some testers, writes to core 1 (PCI-E) instead of core 0 (ChipCommon). -- Vista: [V]iruses, [I]ntruders, [S]pyware, [T]rojans and [A]dware. :-) _______________________________________________ Bcm43xx-dev mailing list Bcm43xx-dev@lists.berlios.de https://lists.berlios.de/mailman/listinfo/bcm43xx-dev
