Chris R. Anderson wrote:
What I'd like to do is run a 64 MHz clock into one of the PLLs on the FPGA, and let the FPGA control the clock speed of the ADC/DAC. That way you have some reasonable control over the sampling rate/bandwidth you want to work with. Ideally, I'd like to be able to process as much bandwidth as possible, but I suspect the limitation will be the interface to the Beagleboard.
Chris, what is your dynamic range requirement? A sampling clock for the ADC derived from a PLL in the FPGA might be too noisy to support a 10-bit ADC, for instance.
Nikhil
