At 07:25 PM 8/5/2008, Nikhil Adnani wrote:
Chris, what is your dynamic range requirement?
A sampling clock for the ADC derived from a PLL in the FPGA might be
too noisy to support a 10-bit ADC, for instance.
Good question. I think going for 10 bits of dynamic range would be a
good target. Looking at the Cyclone III, the PLL jitter spec is +/-
300ps, which is way too large for something like this. I was trying
to avoid using a clock distribution chip (those seem to be expensive
for LVTTL/HCMOS signals), but it doesn't look like I'm going to have
an alternative.
Chris, do you have any price, system performance targets for the board(s)?
I agree with Brian's suggestion below. Also, if you decide you
want a similar feature set to the 9862 but are willing to consider a
lower cost and performance alternative then I would suggest the 9860.
At the moment, we don't have any real "hard" performance goals. I'd
like to be able to get 20 MHz of bandwidth into the FPGA with at
least 10 bits of ADC resolution, and then hopefully get as much of
that as we can squeeze across the interface into the OMAP processor.
As far as a price target, I think with the Beagleboard retailing for
$150, we should probably aim for a bill-of-materials cost (PCB,
parts, and assembly) of less than $200, preferably less than $100
assuming 1k quantities.
At 11:46 AM 8/6/2008, Brian Padalino wrote:
Summarizing a long discussion here:
I am not positive it reduces the risk substantially. I agree it does
reduce risk, but remember the USRP layout is not released - just the
schematics. You'd get the same reference layout design from Analog
Devices as you would for any other converter.
I think it's a good idea to go through some of these lower cost
devices to see if any of their features mesh better with the actual
subset of features being used on the current USRP, the future USRP2
and within GNU Radio.
I think its probably worth doing at least a cursory study of other
ADCs/AFE chips, if only to see what other low-cost options are
available. The big question to answer first is: do we want to stick
with the USRP model (RF downconverter board, ADC on the main board),
or make use of an all-in-one chip, like the Maxim 5163. Those are,
in my mind anyway, two very different design paths.
Personally, I'm leaning towards the USRP model (so that my students
can make use of an existing RF front end, and it leaves open the
possibility for creating a better AFE in the future), and we can
debate about the best choice for ADC/clock speed. Deviating from the
9860/9862 would be fine, it would just mean finding someone that
could figure out how to program/configure the thing. Also, I would
have to be able to get ahold of an eval board either for free or for cheap.
Chris
-------------------------------------
Chris R. Anderson, Ph.D.
[EMAIL PROTECTED]
410-293-6185
Assistant Professor
US Naval Academy
Electrical Engineering Department
105 Maryland Avenue
Annapolis MD 21402
