Alright, I finally got this working, thanks to both William and TJF. In the
end, my problem boils down to coding sloppiness on my part, as well as
being constantly interrupted with other tasks. After spending a solid block
of uninterrupted time doing some careful testing, the following code
snippets are what I found to work. The only device tree overlay I needed is
what I have below; no need to load the BB-ADC overlay.
*PRU Code*
//--------------------------------------------------------------------
// Enable and/or turn on hardware
// Code in this section must be ordered as listed for proper
// hardware startup.
// Enable OCP
lbco r0, PRU_ICSS_CFG_base, PRU_CFG_SYSCFG, 4
clr r0, 4
sbco r0, PRU_ICSS_CFG_base, PRU_CFG_SYSCFG, 4
// Enable ADC clock, wait for ADC module to start before proceeding
mov r0, CM_WKUP_base + CM_WKUP_ADC_TSC_CLKCTRL
mov r1, 2
sbbo r1, r0, 0, 4
mov r1, 0 // clear timeout counter
AdcWait:
LBBO r0, adc_base, ADC_REVISION, 4 // load ADC REVISION
QBNE AdcUp, r0, 0 // exit if ADC is running
ADD r1, r1, 1 // increase timeout counter
QBGE AdcWait, r1.b1, 16 // if no timeout -> wait
AdcUp:
//--------------------------------------------------------------------
*Device Tree* *Overlay*
/dts-v1/;
/plugin/;
/{
compatible = "ti,beaglebone", "ti,beaglebone-black";
part-number = "pru_enable";
version = "00A0";
/* This overlay uses the following resources */
exclusive-use =
"pru0",
"P9.29", // GPIO3[15] fet_off
"P9.30", // GPIO3[16] fet_on
"P9.31"; // GPIO3[14] triac
fragment@0 {
target = <&am33xx_pinmux>;
__overlay__ {
pru_pins: pinmux_pru_pins {
pinctrl-single,pins = <
0x190 0x05 // P9_31 $PINS=100 pr1_pru0_pru_r30_0 mode 5
output pulldown
0x194 0x05 // P9_29 $PINS=101 pr1_pru0_pru_r30_1 mode 5
output pulldown
0x198 0x05 // P9_30 $PINS=102 pr1_pru0_pru_r30_2 mode 5
output pulldown
>;
};
};
};
fragment@2 { // Enable the PRUSS
target = <&pruss>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pru_pins>;
dig_pru_pins {
pin-names = "FET_OFF","FET_ON","TRIAC" ;
gpios = <&gpio3 14 0 // P9.31
&gpio3 15 0 // P9.29
&gpio3 16 0>; // P9.30
};
};
};
};
--
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