I totally get it on the Beaglebone form-factor and continuing support for 
it. I have Beaglebone AI format-type solutions I have to support on the 
software side and the Mech. and Elec. engineers in my group would probably 
devise some kind of torture system and install it in my cubicle if I pushed 
a radically different form factor "just because". I was really only 
parroting what I've observed with the other groups like RPi and the Jetson 
stuff - they seem to be partly going for an industrial direction in a "mass 
quantities" kind of way, doesn't mean that's what the Beagleboard group 
should do at all.

The possibility of expanded I/O would be great to see and PCIe would be 
fantastic even over a "non-standard" connection. I'd also add a vote for a 
populated JTAG connection, or at least one that one that isn't too involved 
to install.


On Thursday, January 14, 2021 at 4:31:32 AM UTC-8 Jason Kridner wrote:

> Yeah, the PRUs are there, but hidden I guess for "support" reasons. I 
> think TI isn't offering the firmware loads to support industrial protocols 
> on this chip to the public. TI already makes a carrier board SOM.  I want 
> to make sure those people who have invested in the BeagleBone form-factor 
> get pay-off with upgraded processing. I'm sure there is lots more that 
> could be done with the TDA4VM. I'm going to try to see if I can at least 
> get a fairly high-speed ribbon cable brought off, but things like PCIe will 
> need to be muxed across type-C in this form-factor as best I can tell.
>
> On Wed, Jan 13, 2021 at 9:19 PM Daniel Kulp <[email protected]> wrote:
>
>> Interesting…. It’s not in the functional diagram.   Awesome that they are 
>> there. 
>>
>> Dan
>>
>>
>>
>> On Jan 13, 2021, at 8:52 PM, Raul Rathmann <[email protected]> wrote:
>>
>> Yes,  what Vinicius said:
>>
>> From TD4VM doc at: https://www.ti.com/product/TDA4VM
>>
>> 7.11.5.24 PRU_ICSSG
>> The device has integrated two identical PRU_ICSSG subsystems (PRU_ICSSG0 
>> and PRU_ICSSG1). The programmable nature of the PRU cores, along with their 
>> access to pins, events and all device resources, provides flexibility in 
>> implementing fast real-time responses, specialized data handling 
>> operations, custom peripheral interfaces, and in offloading tasks from the 
>> other processor cores in the device.  
>>
>> That TD4VM is a real beast. I really look forward to being able to use 
>> the 64-bit ARM cores as the 32-bit Linux world seems to be fading a bit. I 
>> also use the PRUs for low-level I/O, need that hard real-time access.
>>
>> I would really like to see a bunch more I/Os available. The Beaglebone 
>> format is nice size-wise but really seems to constrict access to more of 
>> the IO goodness.
>>
>> Maybe a carrier-board format similar to Pi Compute or Jetson?
>>
>>
>> On Wednesday, January 13, 2021 at 4:27:50 PM UTC-8 [email protected] 
>> wrote:
>>
>>> I was looking the TD4VM and there is 2 prus :)
>>>
>>> Em qua., 13 de jan. de 2021 às 20:43, Vinicius Juvinski <
>>> [email protected]> escreveu:
>>>
>>>> I have the same question as you Daniel,
>>>> the PRU in my opinion is one of the most killer feature of beaglebone 
>>>> and I'm already using BBAI Pru and the 4 PRU's on AI is extremely welcome.
>>>> Jason, any chance to have PRU with this revision 2 BBAI board?
>>>>
>>>> Em qua., 13 de jan. de 2021 às 20:38, Daniel Kulp <[email protected]> 
>>>> escreveu:
>>>>
>>>>> The TDA4VM doesn't have PRU's.   Does that mean use of PRU's is now 
>>>>> "deprecated" and discouraged?
>>>>>
>>>>> Dan
>>>>>
>>>>>
>>>>> On Wednesday, January 13, 2021 at 1:43:02 PM UTC-5 Jason Kridner wrote:
>>>>>
>>>>>> BeagleV is something new in addition to BeagleBoard and BeagleBone 
>>>>>> offerings from BeagleBoard.org. It is meant to address the needs 
>>>>>> coming from the RISC-V community for a low-cost development board, 
>>>>>> ultimately with a path to production. We still have a roadmap for 
>>>>>> BeagleBone!
>>>>>>
>>>>>> So, I'll share what I should have shared before, but am still ironing 
>>>>>> out details on schedule as we are executing this...
>>>>>>
>>>>>> There's a minor tweak to BeagleBone AI rev A1a to rev A2, but I'm not 
>>>>>> sure if it'll go into full production as we have started a rev B with 
>>>>>> the 
>>>>>> TDA4VM device from TI. It jumps to A72s and has better software support 
>>>>>> for 
>>>>>> the AI accelerators.
>>>>>>
>>>>>> One project I'm most excited about is an update to BeagleBone Blue 
>>>>>> (rev C, rev B used the smaller SIP but had unrelated issues that never 
>>>>>> got 
>>>>>> resolved and therefore never got released). I need some more stuff to be 
>>>>>> released from TI to share more details there, but the motor drive 
>>>>>> capability will be boosted to enable direct drive of BLDC quadrotors and 
>>>>>> 3-phase steppers.
>>>>>>
>>>>>> And, I'm very, very excited about BeagleConnect technology being 
>>>>>> worked on at https://github.com/jadonk/beagleconnect based on TI 
>>>>>> CC1352. This still has a long way to productize, but it is really 
>>>>>> interesting tech!
>>>>>>
>>>>>> We also have some cool stuff being worked by BeagleBoard Compatible 
>>>>>> makers in the BeagleBone space. For that matter, SeeedStudio BeagleBone 
>>>>>> Green Gateway hasn't been out very long.
>>>>>>
>>>>>> Anyway, the short answer is BeagleV an in-addition-to-BeagleBone 
>>>>>> thing, not moving away from it.
>>>>>>
>>>>>> If interested in BeagleV, please register your interest at 
>>>>>> BeagleV.org. If you already did so with Seeed, no need to replicate.
>>>>>>
>>>>>> On Wed, Jan 13, 2021 at 8:39 AM [email protected] <
>>>>>> [email protected]> wrote:
>>>>>>
>>>>>>>
>>>>>>> I got a mail message from seeed that introduced the BeagleV. 
>>>>>>>
>>>>>>> Although I am very hopeful for a complete opensource hardware and 
>>>>>>> software platform, I noticed that the pin-layout and the compatibility 
>>>>>>> of 
>>>>>>> the ARM-Beagleboards has been abandoned. 
>>>>>>>
>>>>>>> I also noticed on the specs that the GPIO pins could be used for any 
>>>>>>> kind of communication protocol, be it UART, SPI, SDIO etc. 
>>>>>>>
>>>>>>> I am currently using 3 UART ports on a BeagleBone to communicate 
>>>>>>> with some peripherals. 
>>>>>>>
>>>>>>> Would that still be possible in the new design?
>>>>>>>
>>>>>>> I also noted the RS485, or Canbus was not described in the IO.
>>>>>>>
>>>>>>> Can anyone involved in the design comment on these observations?
>>>>>>> (Why abandon the old pin layout, how to implement three UARTS or 2 
>>>>>>> I2C's, and why no CANBus  availability)
>>>>>>>
>>>>>>> Kind Regards
>>>>>>> Johan Henselmans
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> -- 
>>>>>>> For more options, visit http://beagleboard.org/discuss
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>>>>>>>  
>>>>>>> <https://groups.google.com/d/msgid/beagleboard/3cc933a3-b647-4fe4-b24b-9ba03c478f1fn%40googlegroups.com?utm_medium=email&utm_source=footer>
>>>>>>> .
>>>>>>>
>>>>>>
>>>>>>
>>>>>> -- 
>>>>>> https://beagleboard.org/about/jkridner - a 501c3 non-profit 
>>>>>> educating around open hardware computing
>>>>>>
>>>>>
>>>>> -- 
>>>>> For more options, visit http://beagleboard.org/discuss
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>>>>> You received this message because you are subscribed to the Google 
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>>>>>  
>>>>> <https://groups.google.com/d/msgid/beagleboard/63df07cc-33ac-4be3-8860-93111ccdf3c3n%40googlegroups.com?utm_medium=email&utm_source=footer>
>>>>> .
>>>>>
>>>>
>> -- 
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>> .
>>
>>
>> -- 
>> Daniel Kulp
>> [email protected] - http://dankulp.com/blog 
>>
>> -- 
>> For more options, visit http://beagleboard.org/discuss
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> To view this discussion on the web visit 
>> https://groups.google.com/d/msgid/beagleboard/61128CAB-563B-4FFB-A3A4-5492A5E3068A%40kulp.com
>>  
>> <https://groups.google.com/d/msgid/beagleboard/61128CAB-563B-4FFB-A3A4-5492A5E3068A%40kulp.com?utm_medium=email&utm_source=footer>
>> .
>>
>
>
> -- 
> https://beagleboard.org/about/jkridner - a 501c3 non-profit educating 
> around open hardware computing
>

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