Hi:

I am working with 10.1 library.

For the following code in the adc_interface.vhd

ADC_DATA_DDR: for i in adc_dataeveni'range generate
 adc_dataeveni_ddr: ddr_input port map (
  clk   => adc_clk,
  d     => adc_dataeveni(i),
  qrise => adc_datai_ddr(i + 24),
  qfall => adc_datai_ddr(i +  8)
 );
 adc_dataoddi_ddr: ddr_input port map (
  clk   => adc_clk,
  d     => adc_dataoddi(i),
  qrise => adc_datai_ddr(i + 16),
  qfall => adc_datai_ddr(i +  0)
 );

 adc_dataevenq_ddr: ddr_input port map (
  clk   => adc_clk,
  d     => adc_dataevenq(i),
  qrise => adc_dataq_ddr(i + 24),
  qfall => adc_dataq_ddr(i +  8)
 );
 adc_dataoddq_ddr: ddr_input port map (
  clk   => adc_clk,
  d     => adc_dataoddq(i),
  qrise => adc_dataq_ddr(i + 16),
  qfall => adc_dataq_ddr(i +  0)
 );
end generate;

I only could find bit 15 and 31 are generated in the post map NCD file. I guess 
all others bits are optimized out. I could not understand why.

I could not solve this problem for a week. Anybody has seen this case?

Thanks

Wan

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