Hi David:
Thanks. I checked the map report and it gives me a lot of removing warning.
Some warning are showed here:
WARNING:LIT:243 - Logical network flowtest2_adc_user_data_valid has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1111
more times for the following (max. 5 shown):
flowtest2_adc_user_datai0<0>,
flowtest2_adc_user_datai0<1>,
flowtest2_adc_user_datai0<2>,
flowtest2_adc_user_datai0<3>,
flowtest2_adc_user_datai0<4>
To see the details of these warning messages, please use the -detail switch.
WARNING:MapLib:701 - Signal adc0dataeveni_n<0> connected to top level port
adc0dataeveni_n<0> has been removed.
WARNING:MapLib:701 - Signal adc0dataeveni_n<1> connected to top level port
adc0dataeveni_n<1> has been removed.
WARNING:MapLib:701 - Signal adc0dataeveni_n<2> connected to top level port
adc0dataeveni_n<2> has been removed.
WARNING:MapLib:701 - Signal adc0dataeveni_n<3> connected to top level port
adc0dataeveni_n<3> has been removed.
WARNING:MapLib:701 - Signal adc0dataeveni_n<4> connected to top level port
adc0dataeveni_n<4> has been removed.
WARNING:MapLib:701 - Signal adc0dataeveni_n<5> connected to top level port
adc0dataeveni_n<5> has been removed.
WARNING:MapLib:701 - Signal adc0dataeveni_n<6> connected to top level port
adc0dataeveni_n<6> has been removed.
I checked the MHS file and the connection seems all right. I checked the
synthesis report and all the pins seems available.
But after mapping, it seems that some connections are lost. Not sure why.
And I try to run bee_xps with your mdl file. But before I run it I have to
remove the led GPIO because they are for IBOB and the matlab script is not
happy with those modules. But I still have an error report:
Problem with block :
==============================================================
Simulink Name: rawdata_machine/adc1
Parent System: rawdata_machine
Block type: xps_adc
Ports:
rawdata_machine_adc1_user_data_valid: {[1] 'in' 'user_data_valid'}
rawdata_machine_adc1_user_datai0: {[8] 'in' 'user_datai0'}
rawdata_machine_adc1_user_datai1: {[8] 'in' 'user_datai1'}
rawdata_machine_adc1_user_datai2: {[8] 'in' 'user_datai2'}
rawdata_machine_adc1_user_datai3: {[8] 'in' 'user_datai3'}
rawdata_machine_adc1_user_dataq0: {[8] 'in' 'user_dataq0'}
rawdata_machine_adc1_user_dataq1: {[8] 'in' 'user_dataq1'}
rawdata_machine_adc1_user_dataq2: {[8] 'in' 'user_dataq2'}
rawdata_machine_adc1_user_dataq3: {[8] 'in' 'user_dataq3'}
rawdata_machine_adc1_user_outofrangei0: {[1] 'in' 'user_outofrangei0'}
rawdata_machine_adc1_user_outofrangei1: {[1] 'in' 'user_outofrangei1'}
rawdata_machine_adc1_user_outofrangeq0: {[1] 'in' 'user_outofrangeq0'}
rawdata_machine_adc1_user_outofrangeq1: {[1] 'in' 'user_outofrangeq1'}
rawdata_machine_adc1_user_sync0: {[1] 'in' 'user_sync0'}
rawdata_machine_adc1_user_sync1: {[1] 'in' 'user_sync1'}
rawdata_machine_adc1_user_sync2: {[1] 'in' 'user_sync2'}
rawdata_machine_adc1_user_sync3: {[1] 'in' 'user_sync3'}
hw_sys = ROACH
hw_adc = adc1
adc_clk_rate = 840
adc_interleave = off
adc_str = adc1
==============================================================
Reference to non-existent field 'adc1'.
Error using ==> gen_xps_files at 661
Error found during IP UCF generation in MHS
I have done any mapping or create any bitstream with your mdl file? What's your
experience?
Thanks
Wan.
-----Original Message-----
From: David George [mailto:[email protected]]
Sent: Wednesday, 3 December 2008 6:31 PM
To: Cheng, Wan (ATNF, Marsfield); [email protected]
Subject: Re: [casper] the recapture bits are lost in ADC interface
Hi Wan.
Firstly I'm assuming you are targeting ROACH...
It would probably be best to look at the synthesis/map logs before
looking at the output NCD.
The synthesis logs tend to be very telling when it comes to floating
outputs etc.
Generally speaking when things are optimized away it is an indication
that the outputs are not being used,
so I would check your simulink design and make absolutely sure you are
actually using those signals.
I can confirm that the code from SVN works, attached is a .mdl file for
a design which outputs ADC data to 10Ge.
Note the design will not work without support software to configure the
ADC (currently there is no simple way of
configuring the ADCs)
Regards,
David George
--
David George
Digital Design Engineer
Karoo Array Telescope
Tel: +27 21 531-7282
Fax: +27 21 531-9761
Email: [email protected]
Web: www.ska.ac.za
> Hi:
>
> I am working with 10.1 library.
>
> For the following code in the adc_interface.vhd
>
> ADC_DATA_DDR: for i in adc_dataeveni'range generate
> adc_dataeveni_ddr: ddr_input port map (
> clk => adc_clk,
> d => adc_dataeveni(i),
> qrise => adc_datai_ddr(i + 24),
> qfall => adc_datai_ddr(i + 8)
> );
> adc_dataoddi_ddr: ddr_input port map (
> clk => adc_clk,
> d => adc_dataoddi(i),
> qrise => adc_datai_ddr(i + 16),
> qfall => adc_datai_ddr(i + 0)
> );
>
> adc_dataevenq_ddr: ddr_input port map (
> clk => adc_clk,
> d => adc_dataevenq(i),
> qrise => adc_dataq_ddr(i + 24),
> qfall => adc_dataq_ddr(i + 8)
> );
> adc_dataoddq_ddr: ddr_input port map (
> clk => adc_clk,
> d => adc_dataoddq(i),
> qrise => adc_dataq_ddr(i + 16),
> qfall => adc_dataq_ddr(i + 0)
> );
> end generate;
>
> I only could find bit 15 and 31 are generated in the post map NCD
> file. I guess all others bits are optimized out. I could not
> understand why.
>
> I could not solve this problem for a week. Anybody has seen this case?
>
> Thanks
>
> Wan
